riscv/rocket-chip
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Redo network to use PairedData crossbars when necessary. Hard-coded network types for each message type. Bump chisel, rocket, uncore.

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This commit is contained in:
Henry Cook 2013-05-23 14:55:59 -07:00
parent 6a69d7d7b5
commit c06cbf523b
5 changed files with 163 additions and 209 deletions
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2
chisel

@ -1 +1 @@
Subproject commit cb40a33e5e074643177f69e9e934d4b68c94ebed Subproject commit 2c93b2d07d54e4eaeb7aec347a3fc9f0fec5a48d

2
riscv-rocket

@ -1 +1 @@
Subproject commit 537998adee755201212056b572cb14c3d5af8ed0 Subproject commit 1b6244d6bf61bebbbe9c94a9fc35e7cc414e8959

343
src/main/scala/RocketChip.scala
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@ -11,60 +11,57 @@ import scala.collection.mutable.ArrayBuffer
import scala.collection.mutable.HashMap import scala.collection.mutable.HashMap
object TileLinkHeaderAppender { object TileLinkHeaderAppender {
def apply[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasMemData](meta: ClientSourcedIO[LogicalNetworkIO[T]], data: ClientSourcedIO[LogicalNetworkIO[U]], clientId: Int, addrConvert: (UFix, Int, Int) => UFix)(implicit conf: UncoreConfiguration) = { def apply[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasMemData](in: ClientSourcedDataIO[LogicalNetworkIO[T],LogicalNetworkIO[U]], clientId: Int, nBanks: Int, addrConvert: Bits => UFix)(implicit conf: UncoreConfiguration) = {
val shim = (new TileLinkHeaderAppenderWithData(clientId, addrConvert)){meta.bits.payload.clone}{data.bits.payload.clone} val shim = new TileLinkHeaderAppender(clientId, nBanks, addrConvert)(in.meta.bits.payload.clone, in.data.bits.payload.clone)
shim.io.meta_in <> meta shim.io.in <> in
shim.io.data_in <> data shim.io.out
(shim.io.meta_out, shim.io.data_out)
} }
def apply[T <: SourcedMessage with HasPhysicalAddress](meta: ClientSourcedIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, bankIdLsb: Int)(implicit conf: UncoreConfiguration) = { def apply[T <: SourcedMessage with HasPhysicalAddress](in: ClientSourcedFIFOIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: Bits => UFix)(implicit conf: UncoreConfiguration) = {
val shim = (new TileLinkHeaderAppender(clientId, addrConvert)){meta.bits.payload.clone} val shim = new TileLinkHeaderAppender(clientId, nBanks, addrConvert)(in.bits.payload.clone, new AcquireData)
shim.io.meta_in <> meta shim.io.in.meta <> in
shim.io.meta_out shim.io.out.meta
} }
} }
class TileLinkHeaderAppenderWithData[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasMemData](clientId: Int, addrConvert: (UFix, Int, Int) => UFix)(metadata: => T)(data: => U)(implicit conf: UncoreConfiguration) extends Component{ class TileLinkHeaderAppender[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasMemData](clientId: Int, nBanks: Int, addrConvert: Bits => UFix)(metadata: => T, data: => U)(implicit conf: UncoreConfiguration) extends Component {
implicit val ln = conf.ln implicit val ln = conf.ln
val io = new Bundle { val io = new Bundle {
val meta_in = (new ClientSourcedIO){(new LogicalNetworkIO){ metadata }}.flip val in = new ClientSourcedDataIO()((new LogicalNetworkIO){ metadata }, (new LogicalNetworkIO){ data }).flip
val data_in = (new ClientSourcedIO){(new LogicalNetworkIO){ data }}.flip val out = new ClientSourcedDataIO()((new LogicalNetworkIO){ metadata }, (new LogicalNetworkIO){ data })
val meta_out = (new ClientSourcedIO){(new LogicalNetworkIO){ metadata }}
val data_out = (new ClientSourcedIO){(new LogicalNetworkIO){ data }}
} }
val meta_q = Queue(io.meta_in) val meta_q = Queue(io.in.meta)
val data_q = Queue(io.data_in) val data_q = Queue(io.in.data)
if(nBanks == 1) { if(nBanks == 1) {
io.meta_out.bits.payload := meta_q.bits.payload io.out.meta.bits.payload := meta_q.bits.payload
io.meta_out.bits.header.src := UFix(clientId) io.out.meta.bits.header.src := UFix(clientId)
io.meta_out.bits.header.dst := UFix(0) io.out.meta.bits.header.dst := UFix(0)
io.meta_out.valid := meta_q.valid io.out.meta.valid := meta_q.valid
meta_q.ready := io.meta_out.ready meta_q.ready := io.out.meta.ready
io.data_out.bits.payload := data_q.bits.payload io.out.data.bits.payload := data_q.bits.payload
io.data_out.bits.header.src := UFix(clientId) io.out.data.bits.header.src := UFix(clientId)
io.data_out.bits.header.dst := UFix(0) io.out.data.bits.header.dst := UFix(0)
io.data_out.valid := data_q.valid io.out.data.valid := data_q.valid
data_q.ready := io.data_out.ready data_q.ready := io.out.data.ready
} else { } else {
val meta_has_data = conf.co.messageHasData(meta_q.bits.payload) val meta_has_data = conf.co.messageHasData(meta_q.bits.payload)
val addr_q = (new Queue(2, pipe = true, flow = true)){io.meta_in.bits.payload.addr.clone} val addr_q = (new Queue(2, pipe = true, flow = true)){io.in.meta.bits.payload.addr.clone}
val data_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES))) val data_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
val data_cnt_up = data_cnt + UFix(1) val data_cnt_up = data_cnt + UFix(1)
io.meta_out.bits.payload := meta_q.bits.payload io.out.meta.bits.payload := meta_q.bits.payload
io.meta_out.bits.header.src := UFix(clientId) io.out.meta.bits.header.src := UFix(clientId)
io.meta_out.bits.header.dst := addrConvert(meta_q.bits.payload.addr) io.out.meta.bits.header.dst := addrConvert(meta_q.bits.payload.addr)
io.data_out.bits.payload := meta_q.bits.payload io.out.data.bits.payload := meta_q.bits.payload
io.data_out.bits.header.src := UFix(clientId) io.out.data.bits.header.src := UFix(clientId)
io.data_out.bits.header.dst := addrConvert(addr_q.io.deq.bits) io.out.data.bits.header.dst := addrConvert(addr_q.io.deq.bits)
addr_q.io.enq.bits := meta_q.bits.payload.addr addr_q.io.enq.bits := meta_q.bits.payload.addr
io.meta_out.valid := meta_q.valid && addr_q.io.enq.ready io.out.meta.valid := meta_q.valid && addr_q.io.enq.ready
meta_q.ready := io.meta_out.ready && addr_q.io.enq.ready meta_q.ready := io.out.meta.ready && addr_q.io.enq.ready
io.data_out.valid := data_q.valid && addr_q.io.deq.valid io.out.data.valid := data_q.valid && addr_q.io.deq.valid
data_q.ready := io.data_out.ready && addr_q.io.deq.valid data_q.ready := io.out.data.ready && addr_q.io.deq.valid
addr_q.io.enq.valid := meta_q.valid && io.meta_out.ready && meta_has_data addr_q.io.enq.valid := meta_q.valid && io.out.meta.ready && meta_has_data
addr_q.io.deq.ready := Bool(false) addr_q.io.deq.ready := Bool(false)
when(data_q.valid && data_q.ready) { when(data_q.valid && data_q.ready) {
@ -76,24 +73,6 @@ class TileLinkHeaderAppenderWithData[T <: SourcedMessage with HasPhysicalAddress
} }
} }
class TileLinkHeaderAppender[T <: SourcedMessage with HasPhysicalAddress](clientId: Int, addrConvert: (UFix, Int, Int) => UFix)(metadata: => T)(implicit conf: UncoreConfiguration) extends AddressConverter {
implicit val ln = conf.ln
val io = new Bundle {
val meta_in = (new ClientSourcedIO){(new LogicalNetworkIO){ metadata }}.flip
val meta_out = (new ClientSourcedIO){(new LogicalNetworkIO){ metadata }}
}
val meta_q = Queue(io.meta_in)
io.meta_out.bits.payload := meta_q.bits.payload
io.meta_out.bits.header.src := UFix(clientId)
io.meta_out.valid := meta_q.valid
meta_q.ready := io.meta_out.ready
if(nBanks == 1) {
io.meta_out.bits.header.dst := UFix(0)
} else {
io.meta_out.bits.header.dst := addrConvert(meta_q.bits.payload.addr)
}
}
class MemIOUncachedTileLinkIOConverter(qDepth: Int)(implicit conf: UncoreConfiguration) extends Component { class MemIOUncachedTileLinkIOConverter(qDepth: Int)(implicit conf: UncoreConfiguration) extends Component {
implicit val ln = conf.ln implicit val ln = conf.ln
val io = new Bundle { val io = new Bundle {
@ -102,14 +81,14 @@ class MemIOUncachedTileLinkIOConverter(qDepth: Int)(implicit conf: UncoreConfigu
} }
val mem_cmd_q = (new Queue(qDepth)){new MemReqCmd} val mem_cmd_q = (new Queue(qDepth)){new MemReqCmd}
val mem_data_q = (new Queue(qDepth)){new MemData} val mem_data_q = (new Queue(qDepth)){new MemData}
mem_cmd_q.io.enq.valid := io.uncached.acquire.valid mem_cmd_q.io.enq.valid := io.uncached.acquire.meta.valid
io.uncached.acquire.ready := mem_cmd_q.io.enq.ready io.uncached.acquire.meta.ready := mem_cmd_q.io.enq.ready
mem_cmd_q.io.enq.bits.rw := conf.co.needsOuterWrite(io.uncached.acquire.bits.payload.a_type, UFix(0)) mem_cmd_q.io.enq.bits.rw := conf.co.needsOuterWrite(io.uncached.acquire.meta.bits.payload.a_type, UFix(0))
mem_cmd_q.io.enq.bits.tag := io.uncached.acquire.bits.payload.client_xact_id mem_cmd_q.io.enq.bits.tag := io.uncached.acquire.meta.bits.payload.client_xact_id
mem_cmd_q.io.enq.bits.addr := io.uncached.acquire.bits.payload.addr mem_cmd_q.io.enq.bits.addr := io.uncached.acquire.meta.bits.payload.addr
mem_data_q.io.enq.valid := io.uncached.acquire_data.valid mem_data_q.io.enq.valid := io.uncached.acquire.data.valid
io.uncached.acquire_data.ready := mem_data_q.io.enq.ready io.uncached.acquire.data.ready := mem_data_q.io.enq.ready
mem_data_q.io.enq.bits.data := io.uncached.acquire_data.bits.payload.data mem_data_q.io.enq.bits.data := io.uncached.acquire.data.bits.payload.data
io.uncached.grant.valid := io.mem.resp.valid io.uncached.grant.valid := io.mem.resp.valid
io.mem.resp.ready := io.uncached.grant.ready io.mem.resp.ready := io.uncached.grant.ready
io.uncached.grant.bits.payload.data := io.mem.resp.bits.data io.uncached.grant.bits.payload.data := io.mem.resp.bits.data
@ -120,135 +99,114 @@ class MemIOUncachedTileLinkIOConverter(qDepth: Int)(implicit conf: UncoreConfigu
io.mem.req_data <> mem_data_q.io.deq io.mem.req_data <> mem_data_q.io.deq
} }
object TileToCrossbarShim { class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit conf: UncoreConfiguration) extends LogicalNetwork[TileLinkIO](endpoints)(conf.ln) {
def apply[T <: Data](logIO: ClientSourcedIO[LogicalNetworkIO[T]])(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) = { implicit val lnConf = conf.ln
val shim = (new TileToCrossbarShim) { logIO.bits.payload.clone }
shim.io.in <> logIO
shim.io.out
}
}
class TileToCrossbarShim[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) extends Component {
val io = new Bundle {
val in = (new ClientSourcedIO){(new LogicalNetworkIO){ data }}.flip
val out = (new FIFOIO){(new BasicCrossbarIO){ data }}
}
io.out.bits.header.src := io.in.bits.header.src + UFix(lconf.nMasters)
io.out.bits.header.dst := io.in.bits.header.dst
io.out.bits.payload := io.in.bits.payload
io.out.valid := io.in.valid
io.in.ready := io.out.ready
}
object HubToCrossbarShim {
def apply[T <: Data](logIO: MasterSourcedIO[LogicalNetworkIO[T]])(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) = {
val shim = (new HubToCrossbarShim) { logIO.bits.payload.clone }
shim.io.in <> logIO
shim.io.out
}
}
class HubToCrossbarShim[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) extends Component {
val io = new Bundle {
val in = (new MasterSourcedIO){(new LogicalNetworkIO){ data }}
val out = (new FIFOIO){(new BasicCrossbarIO){ data }}
}
io.out.bits.header.src := io.in.bits.header.src
io.out.bits.header.dst := io.in.bits.header.dst + UFix(lconf.nMasters)
io.out.bits.payload := io.in.bits.payload
io.out.valid := io.in.valid
io.in.ready := io.out.ready
}
object CrossbarToTileShim {
def apply[T <: Data](physIO: FIFOIO[BasicCrossbarIO[T]])(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) = {
val shim = (new CrossbarToTileShim) { physIO.bits.payload.clone }
shim.io.in <> physIO
shim.io.out
}
}
class CrossbarToTileShim[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) extends Component {
val io = new Bundle {
val in = (new FIFOIO){(new BasicCrossbarIO){ data }}.flip
val out = (new ClientSourcedIO){(new LogicalNetworkIO){ data }}
}
io.out.bits.header.src := io.in.bits.header.src
io.out.bits.header.dst := io.in.bits.header.dst - UFix(lconf.nMasters)
io.out.bits.payload := io.in.bits.payload
io.out.valid := io.in.valid
io.in.ready := io.out.ready
}
object CrossbarToHubShim {
def apply[T <: Data](physIO: FIFOIO[BasicCrossbarIO[T]])(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) = {
val shim = (new CrossbarToHubShim) { physIO.bits.payload.clone }
shim.io.in <> physIO
shim.io.out
}
}
class CrossbarToHubShim[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkConfiguration, pconf: PhysicalNetworkConfiguration) extends Component {
val io = new Bundle {
val in = (new FIFOIO){(new BasicCrossbarIO){ data }}.flip
val out = (new MasterSourcedIO){(new LogicalNetworkIO){ data }}.flip
}
io.out.bits.header.src := io.in.bits.header.src - UFix(lconf.nMasters)
io.out.bits.header.dst := io.in.bits.header.dst
io.out.bits.payload := io.in.bits.payload
io.out.valid := io.in.valid
io.in.ready := io.out.ready
}
class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit conf: LogicalNetworkConfiguration) extends LogicalNetwork[TileLinkIO](endpoints)(conf) {
type TileLinkType = TileLinkIO type TileLinkType = TileLinkIO
val io = Vec(endpoints.map(_ match { case t:ClientCoherenceAgent => {(new TileLinkType).flip}; case h:MasterCoherenceAgent => {new TileLinkType}})){ new TileLinkType } val io = Vec(endpoints.map(_ match { case t:ClientCoherenceAgent => {(new TileLinkType).flip}; case h:MasterCoherenceAgent => {new TileLinkType}})){ new TileLinkType }
implicit val pconf = new PhysicalNetworkConfiguration(conf.ln.nEndpoints, conf.ln.idBits) // Same config for all networks
//If we allow all physical networks to be identical, we can use type FBCIO[T <: Data] = FIFOIO[BasicCrossbarIO[T]]
//reflection to automatically create enough networks for any given type FLNIO[T <: Data] = FIFOIO[LogicalNetworkIO[T]]
//bundle containing LogicalNetworkIOs type PBCIO[M <: Data, D <: Data] = PairedDataIO[BasicCrossbarIO[M], BasicCrossbarIO[D]]
val tl = new TileLinkType type PLNIO[M <: Data, D <: Data] = PairedDataIO[LogicalNetworkIO[M], LogicalNetworkIO[D]]
val tileLinkDirectionalFIFOs = tl.getClass.getMethods.filter( x => type FromCrossbar[T <: Data] = FBCIO[T] => FLNIO[T]
classOf[DirectionalFIFOIO[Data]].isAssignableFrom(x.getReturnType)) type ToCrossbar[T <: Data] = FLNIO[T] => FBCIO[T]
val payloadBitsForEachPhysicalNetwork = tileLinkDirectionalFIFOs.map(
_.invoke(tl).asInstanceOf[DirectionalFIFOIO[LogicalNetworkIO[Data]]].bits.payload)
val lockCountForEachPhysicalNetwork = tileLinkDirectionalFIFOs.map( x =>
if(classOf[ClientSourcedDataIO[Data]].isAssignableFrom(x.getReturnType)) REFILL_CYCLES else 1)
implicit val pconf = new PhysicalNetworkConfiguration(conf.nEndpoints, conf.idBits)//same config for all networks
val physicalNetworks: Seq[BasicCrossbar[Data]] = lockCountForEachPhysicalNetwork zip payloadBitsForEachPhysicalNetwork map { case (c,d) => (new BasicCrossbar(c)){d.clone} }
//Use reflection to get the subset of each node's TileLink def DefaultFromCrossbarShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
//corresponding to each direction of dataflow and connect each sub-bundle val out = new FIFOIO()(new LogicalNetworkIO()(in.bits.payload.clone)).asDirectionless
//to the appropriate port of the physical crossbar network, inserting out.bits.header := in.bits.header
//shims to convert headers and process flits in the process. out.bits.payload := in.bits.payload
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => { out.valid := in.valid
val logNetIOSubBundles = io.getClass.getMethods.filter( x => in.ready := out.ready
classOf[DirectionalFIFOIO[Data]].isAssignableFrom(x.getReturnType)).zipWithIndex out
val tileProducedSubBundles = logNetIOSubBundles.filter( x =>
classOf[ClientSourcedIO[Data]].isAssignableFrom(x._1.getReturnType)).map{ case (m,i) =>
(m.invoke(io).asInstanceOf[ClientSourcedIO[LogicalNetworkIO[Data]]],i) }
val hubProducedSubBundles = logNetIOSubBundles.filter( x =>
classOf[MasterSourcedIO[Data]].isAssignableFrom(x._1.getReturnType)).map{ case (m,i) =>
(m.invoke(io).asInstanceOf[MasterSourcedIO[LogicalNetworkIO[Data]]],i) }
end match {
case x:ClientCoherenceAgent => {
tileProducedSubBundles.foreach{ case (sl,i) => {
physicalNetworks(i).io.in(id) <> TileToCrossbarShim(sl)
physicalNetworks(i).io.out(id).ready := Bool(false)
}}
hubProducedSubBundles.foreach{ case (sl,i) => {
sl <> CrossbarToTileShim(physicalNetworks(i).io.out(id))
physicalNetworks(i).io.in(id).valid := Bool(false)
}}
} }
case y:MasterCoherenceAgent => { def CrossbarToMasterShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
hubProducedSubBundles.foreach{ case (sl,i) => { val out = DefaultFromCrossbarShim(in)
physicalNetworks(i).io.in(id) <> HubToCrossbarShim(sl) out.bits.header.src := in.bits.header.src - UFix(conf.ln.nMasters)
physicalNetworks(i).io.out(id).ready := Bool(false) out
}} }
tileProducedSubBundles.foreach{ case (sl,i) => { def CrossbarToClientShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
sl <> CrossbarToHubShim(physicalNetworks(i).io.out(id)) val out = DefaultFromCrossbarShim(in)
physicalNetworks(i).io.in(id).valid := Bool(false) out.bits.header.dst := in.bits.header.dst - UFix(conf.ln.nMasters)
}} out
}
def DefaultToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
val out = new FIFOIO()(new BasicCrossbarIO()(in.bits.payload.clone)).asDirectionless
out.bits.header := in.bits.header
out.bits.payload := in.bits.payload
out.valid := in.valid
in.ready := out.ready
out
}
def MasterToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
val out = DefaultToCrossbarShim(in)
out.bits.header.dst := in.bits.header.dst + UFix(conf.ln.nMasters)
out
}
def ClientToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
val out = DefaultToCrossbarShim(in)
out.bits.header.src := in.bits.header.src + UFix(conf.ln.nMasters)
out
}
def doFIFOInputHookup[T <: Data](phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], shim: ToCrossbar[T]) = {
val s = shim(log_io)
phys_in.valid := s.valid
phys_in.bits := s.bits
s.ready := phys_in.ready
phys_out.ready := Bool(false)
}
def doFIFOOutputHookup[T <: Data](phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], shim: FromCrossbar[T]) = {
val s = shim(phys_out)
log_io.valid := s.valid
log_io.bits := s.bits
s.ready := log_io.ready
phys_in.valid := Bool(false)
}
//TODO: Change all the manifest stuff to use TypeTags in Scala 2.11
def doFIFOHookup[S <: CoherenceAgentRole: ClassManifest, T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], inShim: ToCrossbar[T], outShim: FromCrossbar[T]) = {
if(scala.reflect.ClassManifest.fromClass(end.getClass) <:< classManifest[S]) // end.getClass is a subtype of S
doFIFOInputHookup(phys_in, phys_out, log_io, inShim)
else doFIFOOutputHookup(phys_in, phys_out, log_io, outShim)
}
def doClientSourcedFIFOHookup[T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T]) =
doFIFOHookup[ClientCoherenceAgent, T](end, phys_in, phys_out, log_io, ClientToCrossbarShim, CrossbarToMasterShim)
def doMasterSourcedFIFOHookup[T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T]) =
doFIFOHookup[MasterCoherenceAgent, T](end, phys_in, phys_out, log_io, MasterToCrossbarShim, CrossbarToClientShim)
def doPairedDataHookup[S <: CoherenceAgentRole : ClassManifest, T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R], inShim: ToCrossbar[T], outShim: FromCrossbar[T], inShimD: ToCrossbar[R], outShimD: FromCrossbar[R]) = {
if(scala.reflect.ClassManifest.fromClass(end.getClass) <:< classManifest[S]) {
doFIFOInputHookup[T](phys_in.meta, phys_out.meta, log_io.meta, inShim)
doFIFOInputHookup[R](phys_in.data, phys_out.data, log_io.data, inShimD)
} else {
doFIFOOutputHookup[T](phys_in.meta, phys_out.meta, log_io.meta, outShim)
doFIFOOutputHookup[R](phys_in.data, phys_out.data, log_io.data, outShimD)
} }
} }
}} def doClientSourcedPairedHookup[T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R]) =
doPairedDataHookup[ClientCoherenceAgent, T, R](end, phys_in, phys_out, log_io, ClientToCrossbarShim, CrossbarToMasterShim, ClientToCrossbarShim, CrossbarToMasterShim)
def doMasterSourcedPairedHookup[T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R]) =
doPairedDataHookup[MasterCoherenceAgent, T, R](end, phys_in, phys_out, log_io, MasterToCrossbarShim, CrossbarToClientShim, MasterToCrossbarShim, CrossbarToClientShim)
def acqHasData(acq: BasicCrossbarIO[Acquire]) = conf.co.messageHasData(acq.payload)
val acq_net = new PairedCrossbar(REFILL_CYCLES, acqHasData _)(new Acquire, new AcquireData)
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, acq_net.io.in(id), acq_net.io.out(id), io.acquire) }
def relHasData(rel: BasicCrossbarIO[Release]) = conf.co.messageHasData(rel.payload)
val rel_net = new PairedCrossbar(REFILL_CYCLES, relHasData _)(new Release, new ReleaseData)
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, rel_net.io.in(id), rel_net.io.out(id), io.release) }
val probe_net = new BasicCrossbar()(new Probe)
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doMasterSourcedFIFOHookup(end, probe_net.io.in(id), probe_net.io.out(id), io.probe) }
val grant_net = new BasicCrossbar()(new Grant)
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doMasterSourcedFIFOHookup(end, grant_net.io.in(id), grant_net.io.out(id), io.grant) }
val ack_net = new BasicCrossbar()(new GrantAck)
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedFIFOHookup(end, ack_net.io.in(id), ack_net.io.out(id), io.grant_ack) }
val physicalNetworks = List(acq_net, rel_net, probe_net, grant_net, ack_net)
} }
object ReferenceChipBackend { object ReferenceChipBackend {
@ -334,13 +292,13 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
//val llc = new DRAMSideLLCNull(NGLOBAL_XACTS, REFILL_CYCLES) //val llc = new DRAMSideLLCNull(NGLOBAL_XACTS, REFILL_CYCLES)
val mem_serdes = new MemSerdes(htif_width) val mem_serdes = new MemSerdes(htif_width)
val net = new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints)(lnWithHtifConf) val net = new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints)(ucWithHtifConf)
net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end } net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end }
masterEndpoints.map{ _.io.incoherent zip (io.incoherent ++ List(Bool(true))) map { case (m, c) => m := c } } masterEndpoints.map{ _.io.incoherent zip (io.incoherent ++ List(Bool(true))) map { case (m, c) => m := c } }
val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf) val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf)
if(lnWithHtifConf.nMasters > 1) { if(lnWithHtifConf.nMasters > 1) {
val arb = new UncachedTileLinkIOArbiter(lnWithHtifConf.nMasters)(lnWithHtifConf) val arb = new UncachedTileLinkIOArbiter(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache } arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
conv.io.uncached <> arb.io.out conv.io.uncached <> arb.io.out
} else { } else {
@ -405,13 +363,8 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
(outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map { (outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map {
case ((outer, client), i) => case ((outer, client), i) =>
val (acq_w_header, acq_data_w_header) = TileLinkHeaderAppender(client.acquire, client.acquire_data, i, convertAddrToBank) outer.acquire <> TileLinkHeaderAppender(client.acquire, i, nBanks, convertAddrToBank _)
outer.acquire <> acq_w_header outer.release <> TileLinkHeaderAppender(client.release, i, nBanks, convertAddrToBank _)
outer.acquire_data <> acq_data_w_header
val (rel_w_header, rel_data_w_header) = TileLinkHeaderAppender(client.release, client.release_data, i, convertAddrToBank)
outer.release <> rel_w_header
outer.release_data <> rel_data_w_header
val grant_ack_q = Queue(client.grant_ack) val grant_ack_q = Queue(client.grant_ack)
outer.grant_ack.valid := grant_ack_q.valid outer.grant_ack.valid := grant_ack_q.valid

19
src/main/scala/fpga.scala
View File

@ -25,13 +25,13 @@ class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenc
require(clientEndpoints.length == lnWithHtifConf.nClients) require(clientEndpoints.length == lnWithHtifConf.nClients)
val masterEndpoints = (0 until lnWithHtifConf.nMasters).map(new L2CoherenceAgent(_)(ucWithHtifConf)) val masterEndpoints = (0 until lnWithHtifConf.nMasters).map(new L2CoherenceAgent(_)(ucWithHtifConf))
val net = new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints)(lnWithHtifConf) val net = new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints)(ucWithHtifConf)
net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end } net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end }
masterEndpoints.map{ _.io.incoherent zip (io.incoherent ++ List(Bool(true))) map { case (m, c) => m := c } } masterEndpoints.map{ _.io.incoherent zip (io.incoherent ++ List(Bool(true))) map { case (m, c) => m := c } }
val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf) val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf)
if(lnWithHtifConf.nMasters > 1) { if(lnWithHtifConf.nMasters > 1) {
val arb = new UncachedTileLinkIOArbiter(lnWithHtifConf.nMasters)(lnWithHtifConf) val arb = new UncachedTileLinkIOArbiter(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache } arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
conv.io.uncached <> arb.io.out conv.io.uncached <> arb.io.out
} else { } else {
@ -63,15 +63,16 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit
io.mem <> outmemsys.io.mem io.mem <> outmemsys.io.mem
// Add networking headers and endpoint queues // Add networking headers and endpoint queues
// Add networking headers and endpoint queues
def convertAddrToBank(addr: Bits): UFix = {
require(bankIdLsb + log2Up(nBanks) < PADDR_BITS - OFFSET_BITS, {println("Invalid bits for bank multiplexing.")})
addr(bankIdLsb + log2Up(nBanks) - 1, bankIdLsb)
}
(outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map { (outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map {
case ((outer, client), i) => case ((outer, client), i) =>
val (acq_w_header, acq_data_w_header) = TileLinkHeaderAppender(client.acquire, client.acquire_data, i, nBanks, bankIdLsb) outer.acquire <> TileLinkHeaderAppender(client.acquire, i, nBanks, convertAddrToBank _)
outer.acquire <> acq_w_header outer.release <> TileLinkHeaderAppender(client.release, i, nBanks, convertAddrToBank _)
outer.acquire_data <> acq_data_w_header
val (rel_w_header, rel_data_w_header) = TileLinkHeaderAppender(client.release, client.release_data, i, nBanks, bankIdLsb)
outer.release <> rel_w_header
outer.release_data <> rel_data_w_header
val grant_ack_q = Queue(client.grant_ack) val grant_ack_q = Queue(client.grant_ack)
outer.grant_ack.valid := grant_ack_q.valid outer.grant_ack.valid := grant_ack_q.valid

2
uncore

@ -1 +1 @@
Subproject commit 711337a644363cce1e542af05988b326a95f2697 Subproject commit f238f04fd9cd9751a515a129e474d4ffc8631817