riscv/rocket-chip
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Modify the RoCC interface to include status in the command queue. (#41)

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This addresses a bug in which changes in mstatus could
propagate to RoCCs before their time. Existing RoCCs that use
the status port will need to be modified to match this change.

This addresses the first half of #40.
This commit is contained in:
Ben Keller 2016-07-18 17:40:50 -07:00 committed by Andrew Waterman
parent 2723b2f515
commit c069e66056
3 changed files with 2 additions and 3 deletions
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2
rocket/src/main/scala/rocc.scala
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@ -37,6 +37,7 @@ class RoCCCommand(implicit p: Parameters) extends CoreBundle()(p) {
val inst = new RoCCInstruction val inst = new RoCCInstruction
val rs1 = Bits(width = xLen) val rs1 = Bits(width = xLen)
val rs2 = Bits(width = xLen) val rs2 = Bits(width = xLen)
val status = new MStatus
} }
class RoCCResponse(implicit p: Parameters) extends CoreBundle()(p) { class RoCCResponse(implicit p: Parameters) extends CoreBundle()(p) {
@ -49,7 +50,6 @@ class RoCCInterface(implicit p: Parameters) extends CoreBundle()(p) {
val resp = Decoupled(new RoCCResponse) val resp = Decoupled(new RoCCResponse)
val mem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" })) val mem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" }))
val busy = Bool(OUTPUT) val busy = Bool(OUTPUT)
val status = new MStatus().asInput
val interrupt = Bool(OUTPUT) val interrupt = Bool(OUTPUT)
// These should be handled differently, eventually // These should be handled differently, eventually

2
rocket/src/main/scala/rocket.scala
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@ -599,7 +599,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common
io.rocc.exception := wb_xcpt && csr.io.status.xs.orR io.rocc.exception := wb_xcpt && csr.io.status.xs.orR
io.rocc.status := csr.io.status io.rocc.cmd.bits.status := csr.io.status
io.rocc.cmd.bits.inst := new RoCCInstruction().fromBits(wb_reg_inst) io.rocc.cmd.bits.inst := new RoCCInstruction().fromBits(wb_reg_inst)
io.rocc.cmd.bits.rs1 := wb_reg_wdata io.rocc.cmd.bits.rs1 := wb_reg_wdata
io.rocc.cmd.bits.rs2 := wb_reg_rs2 io.rocc.cmd.bits.rs2 := wb_reg_rs2

1
rocket/src/main/scala/tile.scala
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@ -76,7 +76,6 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
})) }))
val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams)) val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
rocc.io.cmd <> cmdRouter.io.out(i) rocc.io.cmd <> cmdRouter.io.out(i)
rocc.io.status := core.io.rocc.status
rocc.io.exception := core.io.rocc.exception rocc.io.exception := core.io.rocc.exception
rocc.io.host_id := io.prci.id rocc.io.host_id := io.prci.id
dcIF.io.requestor <> rocc.io.mem dcIF.io.requestor <> rocc.io.mem