From c069e660568a3ddbdb2e72384ee50ab2387601eb Mon Sep 17 00:00:00 2001
From: Ben Keller <bkeller@eecs.berkeley.edu>
Date: Mon, 18 Jul 2016 17:40:50 -0700
Subject: [PATCH] Modify the RoCC interface to include status in the command
 queue. (#41)

This addresses a bug in which changes in mstatus could
propagate to RoCCs before their time. Existing RoCCs that use
the status port will need to be modified to match this change.

This addresses the first half of #40.
---
 rocket/src/main/scala/rocc.scala   | 2 +-
 rocket/src/main/scala/rocket.scala | 2 +-
 rocket/src/main/scala/tile.scala   | 1 -
 3 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/rocket/src/main/scala/rocc.scala b/rocket/src/main/scala/rocc.scala
index e8e5e626..ce0fcfbe 100644
--- a/rocket/src/main/scala/rocc.scala
+++ b/rocket/src/main/scala/rocc.scala
@@ -37,6 +37,7 @@ class RoCCCommand(implicit p: Parameters) extends CoreBundle()(p) {
   val inst = new RoCCInstruction
   val rs1 = Bits(width = xLen)
   val rs2 = Bits(width = xLen)
+  val status = new MStatus
 }
 
 class RoCCResponse(implicit p: Parameters) extends CoreBundle()(p) {
@@ -49,7 +50,6 @@ class RoCCInterface(implicit p: Parameters) extends CoreBundle()(p) {
   val resp = Decoupled(new RoCCResponse)
   val mem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" }))
   val busy = Bool(OUTPUT)
-  val status = new MStatus().asInput
   val interrupt = Bool(OUTPUT)
   
   // These should be handled differently, eventually
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index 4e1e7582..7756ab18 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -599,7 +599,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
 
   io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common
   io.rocc.exception := wb_xcpt && csr.io.status.xs.orR
-  io.rocc.status := csr.io.status
+  io.rocc.cmd.bits.status := csr.io.status
   io.rocc.cmd.bits.inst := new RoCCInstruction().fromBits(wb_reg_inst)
   io.rocc.cmd.bits.rs1 := wb_reg_wdata
   io.rocc.cmd.bits.rs2 := wb_reg_rs2
diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index ee154ee8..9f635663 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -76,7 +76,6 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
       }))
       val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
       rocc.io.cmd <> cmdRouter.io.out(i)
-      rocc.io.status := core.io.rocc.status
       rocc.io.exception := core.io.rocc.exception
       rocc.io.host_id := io.prci.id
       dcIF.io.requestor <> rocc.io.mem