riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache

Browse Source
This commit is contained in:
Yunsup Lee
2012-02-26 23:46:51 -08:00
parent 6e706c7c74
commit bfd0ae125e
5 changed files with 25 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/dpath.scala
View File

@ -19,7 +19,7 @@ class ioDpathAll extends Bundle()
val ctrl = new ioCtrlDpath().flip();
val debug = new ioDebug();
val dmem = new ioDmem(List("req_idx", "req_tag", "req_data", "resp_val", "resp_miss", "resp_replay", "resp_type", "resp_tag", "resp_data", "resp_data_subword")).flip();
val dtlb = new ioDTLB_CPU_req_bundle(List("vpn"))
val dtlb = new ioDTLB_CPU_req_bundle().asOutput()
val imem = new ioDpathImem();
val ptbr_wen = Bool(OUTPUT);
val ptbr = UFix(PADDR_BITS, OUTPUT);