riscv/rocket-chip
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Add ShiftQueue; use it

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Andrew Waterman
2017-04-21 18:01:09 -07:00
committed by Andrew Waterman
parent d24d8ff84b
commit bf861293d9
2 changed files with 62 additions and 1 deletions
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2
src/main/scala/rocket/Frontend.scala
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@ -65,7 +65,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
val icache = outer.icache.module
val tlb = Module(new TLB(log2Ceil(coreInstBytes*fetchWidth), nTLBEntries))
val fq = withReset(reset || io.cpu.req.valid) { Module(new Queue(new FrontendResp, 3, flow = true)) }
val fq = withReset(reset || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 3, flow = true)) }
val s0_valid = io.cpu.req.valid || fq.io.enq.ready
val s1_pc_ = Reg(UInt(width=vaddrBitsExtended))