riscv/rocket-chip
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rocketchip: relax mmio no-interleaving requirement

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This commit is contained in:
Wesley W. Terpstra 2017-04-21 17:13:09 -07:00
parent 24f577c156
commit bf5cb396b9
1 changed files with 3 additions and 4 deletions
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src/main/scala/rocketchip/Periphery.scala
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@ -202,16 +202,15 @@ trait PeripheryMasterAXI4MMIO {
resources = device.reg, resources = device.reg,
executable = true, // Can we run programs on this memory? executable = true, // Can we run programs on this memory?
supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
supportsRead = TransferSizes(1, 256), supportsRead = TransferSizes(1, 256))),
interleavedId = Some(0))), // slave does not interleave read responses
beatBytes = config.beatBytes))) beatBytes = config.beatBytes)))
mmio_axi4 := mmio_axi4 :=
AXI4Buffer()( AXI4Buffer()(
// AXI4Fragmenter(lite=false, maxInFlight = 20)( // beef device up to support awlen = 0xff AXI4Deinterleaver(cacheBlockBytes)(
TLToAXI4(idBits = config.idBits)( // use idBits = 0 for AXI4-Lite TLToAXI4(idBits = config.idBits)( // use idBits = 0 for AXI4-Lite
TLWidthWidget(socBusConfig.beatBytes)( // convert width before attaching to socBus TLWidthWidget(socBusConfig.beatBytes)( // convert width before attaching to socBus
socBus.node))) socBus.node))))
} }
trait PeripheryMasterAXI4MMIOBundle { trait PeripheryMasterAXI4MMIOBundle {