From bf5cb396b956a93d9f6f49171544c46cb8282e65 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 21 Apr 2017 17:13:09 -0700 Subject: [PATCH] rocketchip: relax mmio no-interleaving requirement --- src/main/scala/rocketchip/Periphery.scala | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala index 7d29c8cc..92bbbd76 100644 --- a/src/main/scala/rocketchip/Periphery.scala +++ b/src/main/scala/rocketchip/Periphery.scala @@ -202,16 +202,15 @@ trait PeripheryMasterAXI4MMIO { resources = device.reg, executable = true, // Can we run programs on this memory? supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers - supportsRead = TransferSizes(1, 256), - interleavedId = Some(0))), // slave does not interleave read responses + supportsRead = TransferSizes(1, 256))), beatBytes = config.beatBytes))) mmio_axi4 := AXI4Buffer()( - // AXI4Fragmenter(lite=false, maxInFlight = 20)( // beef device up to support awlen = 0xff + AXI4Deinterleaver(cacheBlockBytes)( TLToAXI4(idBits = config.idBits)( // use idBits = 0 for AXI4-Lite TLWidthWidget(socBusConfig.beatBytes)( // convert width before attaching to socBus - socBus.node))) + socBus.node)))) } trait PeripheryMasterAXI4MMIOBundle {