riscv/rocket-chip
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make sure PTE cache is power of 2 in size to satisfy PseudoLRU requirement

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This commit is contained in:
Howard Mao 2016-07-27 18:40:38 -07:00
parent dcfcac9530
commit bf35f980a6
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/ptw.scala
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@ -98,7 +98,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
} }
val (pte_cache_hit, pte_cache_data) = { val (pte_cache_hit, pte_cache_data) = {
val size = log2Up(pgLevels * 2) val size = 1 << log2Up(pgLevels * 2)
val plru = new PseudoLRU(size) val plru = new PseudoLRU(size)
val valid = Reg(init = UInt(0, size)) val valid = Reg(init = UInt(0, size))
val tags = Reg(Vec(size, UInt(width = paddrBits))) val tags = Reg(Vec(size, UInt(width = paddrBits)))