From bf35f980a6a1266ede76cd130c51503c2f3b3dc8 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Wed, 27 Jul 2016 18:40:38 -0700 Subject: [PATCH] make sure PTE cache is power of 2 in size to satisfy PseudoLRU requirement --- rocket/src/main/scala/ptw.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala index 9a431618..c5a64764 100644 --- a/rocket/src/main/scala/ptw.scala +++ b/rocket/src/main/scala/ptw.scala @@ -98,7 +98,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) { } val (pte_cache_hit, pte_cache_data) = { - val size = log2Up(pgLevels * 2) + val size = 1 << log2Up(pgLevels * 2) val plru = new PseudoLRU(size) val valid = Reg(init = UInt(0, size)) val tags = Reg(Vec(size, UInt(width = paddrBits)))