Refactor to combine fpga and vlsi tops, part 1
This commit is contained in:
Henry Cook
parent
a41d55b643
commit
bf356b9cb4
@ -11,6 +11,23 @@ class DefaultCPPConfig extends DefaultConfig
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class DefaultConfig extends ChiselConfig {
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val top:World.TopDefs = {
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(pname,site,here) => pname match {
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//HTIF Parameters
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case HTIFWidth => 16
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case HTIFNSCR => 64
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case HTIFOffsetBits => site(CacheBlockOffsetBits)
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case HTIFNCores => site(NTiles)
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//Memory Parameters
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case PAddrBits => 32
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case VAddrBits => 43
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case PgIdxBits => 13
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case ASIdBits => 7
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case PermBits => 6
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case PPNBits => site(PAddrBits) - site(PgIdxBits)
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case VPNBits => site(VAddrBits) - site(PgIdxBits)
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case MIFTagBits => 5
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case MIFDataBits => 128
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case MIFAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
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case MIFDataBeats => site(TLDataBits)/site(MIFDataBits)
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//Params used by all caches
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case ECCCode => None
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case WordBits => site(XprLen)
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@ -21,12 +38,12 @@ class DefaultConfig extends ChiselConfig {
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}
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case NSets => site(CacheName) match {
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case "L1I" => 128
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case "L1D" => 128
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case "L1D" => Knob("L1D_SETS") //128
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case "L2" => 512
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}
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case NWays => site(CacheName) match {
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case "L1I" => 2
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case "L1D" => 4
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case "L1D" => Knob("L1D_WAYS") //4
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case "L2" => 8
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}
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case RowBits => site(CacheName) match {
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@ -42,11 +59,11 @@ class DefaultConfig extends ChiselConfig {
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case NDTLBEntries => 8
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case StoreDataQueueDepth => 17
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case ReplayQueueDepth => 16
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case NMSHRs => site[Int]("NMSHRS")
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case NMSHRs => Knob("L1D_MSHRS")
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case LRSCCycles => 32
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//L2CacheParams
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case NReleaseTransactors => site[Int]("NL2_REL_XACTS")
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case NAcquireTransactors => site[Int]("NL2_ACQ_XACTS")
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case NReleaseTransactors => Knob("L2_REL_XACTS")
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case NAcquireTransactors => Knob("L2_ACQ_XACTS")
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case NClients => site(NTiles) + 1
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//Tile Constants
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case BuildRoCC => None
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@ -67,23 +84,6 @@ class DefaultConfig extends ChiselConfig {
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case CoreInstBits => 32
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case CoreDataBits => site(XprLen)
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case CoreDCacheReqTagBits => 7 + log2Up(here(NDCachePorts))
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//HTIF Parameters
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case HTIFWidth => 16
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case HTIFNSCR => 64
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case HTIFOffsetBits => site(CacheBlockOffsetBits)
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case HTIFNCores => site(NTiles)
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//Memory Parameters
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case PAddrBits => 32
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case VAddrBits => 43
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case PgIdxBits => 13
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case ASIdBits => 7
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case PermBits => 6
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case PPNBits => site(PAddrBits) - site(PgIdxBits)
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case VPNBits => site(VAddrBits) - site(PgIdxBits)
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case MIFTagBits => 5
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case MIFDataBits => 128
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case MIFAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
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case MIFDataBeats => 4
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//Uncore Paramters
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case LNMasters => site(NBanks)
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case LNClients => site(NTiles)+1
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@ -96,13 +96,13 @@ class DefaultConfig extends ChiselConfig {
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case TLWriteMaskBits => 6
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case TLWordAddrBits => 3
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case TLAtomicOpBits => 4
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case NTiles => here[Int]("NTILES")
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case NBanks => here[Int]("NBANKS")
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case NTiles => Knob("NTILES")
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case NBanks => Knob("NBANKS")
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case BankIdLSB => 5
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case CacheBlockBytes => 64
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case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
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case BuildDRAMSideLLC => () => {
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val refill = site(TLDataBits)/site(MIFDataBits)
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case UseBackupMemoryPort => true
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case BuildDRAMSideLLC => (refill: Int) => {
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if(site[Boolean]("USE_DRAMSIDE_LLC")) {
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val tag = Mem(Bits(width = 152), 512, seqRead = true)
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val data = Mem(Bits(width = 64), 4096, seqRead = true)
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@ -110,11 +110,11 @@ class DefaultConfig extends ChiselConfig {
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refill_cycles=refill, tagLeaf=tag, dataLeaf=data))
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} else { Module(new DRAMSideLLCNull(16, refill)) }
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}
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case BuildCoherentMaster => (id: Int) => {
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if(!site[Boolean]("USE_DRAMSIDE_LLC")) {
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Module(new L2CoherenceAgent(id), { case CacheName => "L2" })
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} else {
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case BuildCoherenceMaster => (id: Int) => {
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if(site[Boolean]("USE_L2_CACHE")) {
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Module(new L2HellaCache(id), { case CacheName => "L2" })
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} else {
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Module(new L2CoherenceAgent(id), { case CacheName => "L2" })
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}
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}
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case Coherence => {
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@ -129,17 +129,20 @@ class DefaultConfig extends ChiselConfig {
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else new MICoherence(dir)
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}
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}
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//DesignSpaceConstants //TODO KNOBS
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case "NTILES" => 1
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case "NBANKS" => 1
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case "HTIF_WIDTH" => 16
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case "ENABLE_SHARING" => true
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case "ENABLE_CLEAN_EXCLUSIVE" => true
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case "USE_DRAMSIDE_LLC" => true
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case "NL2_REL_XACTS" => 1
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case "NL2_ACQ_XACTS" => 7
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case "NMSHRS" => 2
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case "USE_L2_CACHE" => false
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}
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}
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override val knobVal:Any=>Any = {
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case "NTILES" => 1
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case "NBANKS" => 1
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case "L2_REL_XACTS" => 1
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case "L2_ACQ_XACTS" => 7
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case "L1D_MSHRS" => 2
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case "L1D_SETS" => 128
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case "L1D_WAYS" => 4
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}
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}
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@ -10,12 +10,19 @@ case object NBanks extends Field[Int]
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case object BankIdLSB extends Field[Int]
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case object CacheBlockBytes extends Field[Int]
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case object CacheBlockOffsetBits extends Field[Int]
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case object BuildDRAMSideLLC extends Field[() => DRAMSideLLCLike]
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case object BuildCoherentMaster extends Field[(Int) => CoherenceAgent]
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case object BuildDRAMSideLLC extends Field[(Int) => DRAMSideLLCLike]
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case object BuildCoherenceMaster extends Field[(Int) => CoherenceAgent]
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case object UseBackupMemoryPort extends Field[Boolean]
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case object Coherence extends Field[CoherencePolicyWithUncached]
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class OuterMemorySystem extends Module
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{
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abstract trait TopLevelParameters extends UsesParameters {
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val htifW = params(HTIFWidth)
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val nTiles = params(NTiles)
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val nBanks = params(NBanks)
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val lsb = params(BankIdLSB)
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val refillCycles = params(MIFDataBeats)
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}
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class OuterMemorySystem extends Module with TopLevelParameters {
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val io = new Bundle {
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val tiles = Vec.fill(params(NTiles)){new TileLinkIO}.flip
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val htif = (new TileLinkIO).flip
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@ -25,15 +32,14 @@ class OuterMemorySystem extends Module
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val mem_backup_en = Bool(INPUT)
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}
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val refill_cycles = params(TLDataBits)/params(MIFDataBits)
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val llc = params(BuildDRAMSideLLC)()
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val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherentMaster))
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// Create a simple NoC and points of coherence serialization
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val net = Module(new ReferenceChipCrossbarNetwork)
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val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherenceMaster))
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net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
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net.io.masters zip (masterEndpoints.map(_.io.inner)) map { case (net, end) => net <> end }
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masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
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// Create a converter between TileLinkIO and MemIO
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val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
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if(params(NBanks) > 1) {
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val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(params(NBanks)))
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@ -42,107 +48,75 @@ class OuterMemorySystem extends Module
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} else {
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conv.io.uncached <> masterEndpoints.head.io.outer
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}
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llc.io.cpu.req_cmd <> Queue(conv.io.mem.req_cmd)
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llc.io.cpu.req_data <> Queue(conv.io.mem.req_data, refill_cycles)
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// Create a DRAM-side LLC
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val llc = params(BuildDRAMSideLLC)(refillCycles)
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llc.io.cpu.req_cmd <> Queue(conv.io.mem.req_cmd, 2)
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llc.io.cpu.req_data <> Queue(conv.io.mem.req_data, refillCycles)
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conv.io.mem.resp <> llc.io.cpu.resp
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// mux between main and backup memory ports
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val mem_serdes = Module(new MemSerdes(params(HTIFWidth)))
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val mem_cmdq = Module(new Queue(new MemReqCmd, 2))
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mem_cmdq.io.enq <> llc.io.mem.req_cmd
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mem_cmdq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_cmd.ready, io.mem.req_cmd.ready)
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io.mem.req_cmd.valid := mem_cmdq.io.deq.valid && !io.mem_backup_en
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io.mem.req_cmd.bits := mem_cmdq.io.deq.bits
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mem_serdes.io.wide.req_cmd.valid := mem_cmdq.io.deq.valid && io.mem_backup_en
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mem_serdes.io.wide.req_cmd.bits := mem_cmdq.io.deq.bits
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val mem_dataq = Module(new Queue(new MemData, refill_cycles))
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mem_dataq.io.enq <> llc.io.mem.req_data
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mem_dataq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_data.ready, io.mem.req_data.ready)
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io.mem.req_data.valid := mem_dataq.io.deq.valid && !io.mem_backup_en
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io.mem.req_data.bits := mem_dataq.io.deq.bits
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mem_serdes.io.wide.req_data.valid := mem_dataq.io.deq.valid && io.mem_backup_en
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mem_serdes.io.wide.req_data.bits := mem_dataq.io.deq.bits
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llc.io.mem.resp.valid := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.valid, io.mem.resp.valid)
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io.mem.resp.ready := Bool(true)
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llc.io.mem.resp.bits := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.bits, io.mem.resp.bits)
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io.mem_backup <> mem_serdes.io.narrow
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// Create a SerDes for backup memory port
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if(params(UseBackupMemoryPort)) {
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VLSIUtils.doOuterMemorySystemSerdes(llc.io.mem, io.mem, io.mem_backup,
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io.mem_backup_en, params(HTIFWidth))
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} else {
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io.mem <> llc.io.mem
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}
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}
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class Uncore extends Module
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{
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require(params(BankIdLSB) + log2Up(params(NBanks)) < params(MIFAddrBits))
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val htif_width = params(HTIFWidth)
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class Uncore extends Module with TopLevelParameters {
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val io = new Bundle {
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val host = new HostIO(htif_width)
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val host = new HostIO
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val mem = new MemIO
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val tiles = Vec.fill(params(NTiles)){new TileLinkIO}.flip
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val htif = Vec.fill(params(NTiles)){new HTIFIO}.flip
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val incoherent = Vec.fill(params(NTiles)){Bool()}.asInput
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val mem_backup = new MemSerializedIO(htif_width)
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val tiles = Vec.fill(nTiles){new TileLinkIO}.flip
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val htif = Vec.fill(nTiles){new HTIFIO}.flip
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val incoherent = Vec.fill(nTiles){Bool()}.asInput
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val mem_backup = new MemSerializedIO(htifW)
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val mem_backup_en = Bool(INPUT)
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}
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val htif = Module(new HTIF(CSRs.reset))
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val outmemsys = Module(new OuterMemorySystem)
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val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
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outmemsys.io.incoherent := incoherentWithHtif
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htif.io.cpu <> io.htif
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outmemsys.io.mem <> io.mem
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outmemsys.io.mem_backup_en <> io.mem_backup_en
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// Add networking headers and endpoint queues
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def convertAddrToBank(addr: Bits): UInt = {
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addr(params(BankIdLSB) + log2Up(params(NBanks)) - 1, params(BankIdLSB))
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// Used to hash physical addresses to banks
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require(params(BankIdLSB) + log2Up(params(NBanks)) < params(MIFAddrBits))
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def addrToBank(addr: Bits): UInt = {
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if(nBanks > 1) addr( lsb + log2Up(nBanks) - 1, lsb)
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else UInt(0)
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}
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(outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map {
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case ((outer, client), i) =>
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outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, params(NBanks), convertAddrToBank _))
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outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, params(NBanks), convertAddrToBank _))
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val htif = Module(new HTIF(CSRs.reset)) // One HTIF module per chip
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val outmemsys = Module(new OuterMemorySystem) // NoC, LLC and SerDes
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// Wire outer mem system to tiles and htif, adding
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// networking headers and endpoint queues
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(outmemsys.io.tiles :+ outmemsys.io.htif) // Collect outward-facing TileLink ports
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.zip(io.tiles :+ htif.io.mem) // Zip them with matching ports from clients
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.zipWithIndex // Index them
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.map { case ((outer, client), i) => // Then use the index and bank hash to
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// overwrite the networking header
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outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, nBanks, addrToBank _))
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outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, nBanks, addrToBank _))
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outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i, true))
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client.grant <> Queue(outer.grant, 1, pipe = true)
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client.probe <> Queue(outer.probe)
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}
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// pad out the HTIF using a divided clock
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val hio = Module((new SlowIO(512)) { Bits(width = params(HTIFWidth)+1) })
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hio.io.set_divisor.valid := htif.io.scr.wen && htif.io.scr.waddr === 63
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hio.io.set_divisor.bits := htif.io.scr.wdata
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htif.io.scr.rdata(63) := hio.io.divisor
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hio.io.out_fast.valid := htif.io.host.out.valid || outmemsys.io.mem_backup.req.valid
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hio.io.out_fast.bits := Cat(htif.io.host.out.valid, Mux(htif.io.host.out.valid, htif.io.host.out.bits, outmemsys.io.mem_backup.req.bits))
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htif.io.host.out.ready := hio.io.out_fast.ready
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outmemsys.io.mem_backup.req.ready := hio.io.out_fast.ready && !htif.io.host.out.valid
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io.host.out.valid := hio.io.out_slow.valid && hio.io.out_slow.bits(htif_width)
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io.host.out.bits := hio.io.out_slow.bits
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io.mem_backup.req.valid := hio.io.out_slow.valid && !hio.io.out_slow.bits(htif_width)
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hio.io.out_slow.ready := Mux(hio.io.out_slow.bits(htif_width), io.host.out.ready, io.mem_backup.req.ready)
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val mem_backup_resp_valid = io.mem_backup_en && io.mem_backup.resp.valid
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hio.io.in_slow.valid := mem_backup_resp_valid || io.host.in.valid
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hio.io.in_slow.bits := Cat(mem_backup_resp_valid, io.host.in.bits)
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io.host.in.ready := hio.io.in_slow.ready
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outmemsys.io.mem_backup.resp.valid := hio.io.in_fast.valid && hio.io.in_fast.bits(htif_width)
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outmemsys.io.mem_backup.resp.bits := hio.io.in_fast.bits
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htif.io.host.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htif_width)
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htif.io.host.in.bits := hio.io.in_fast.bits
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hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htif_width), Bool(true), htif.io.host.in.ready)
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io.host.clk := hio.io.clk_slow
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io.host.clk_edge := Reg(next=io.host.clk && !Reg(next=io.host.clk))
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}
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outmemsys.io.incoherent := (io.incoherent :+ Bool(true).asInput)
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// Wire the htif to the memory port(s) and host interface
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io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr
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htif.io.cpu <> io.htif
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outmemsys.io.mem <> io.mem
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if(params(UseBackupMemoryPort)) {
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outmemsys.io.mem_backup_en := io.mem_backup_en
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VLSIUtils.padOutHTIFWithDividedClock(htif.io, outmemsys.io.mem_backup,
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io.mem_backup, io.host, io.mem_backup_en, htifW)
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} else {
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htif.io.host.out <> io.host.out
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htif.io.host.in <> io.host.in
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}
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}
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class TopIO extends Bundle {
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val host = new HostIO(params(HTIFWidth))
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class TopIO extends Bundle {
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val host = new HostIO
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val mem = new MemIO
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}
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class VLSITopIO extends TopIO {
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val mem_backup_en = Bool(INPUT)
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val in_mem_ready = Bool(OUTPUT)
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val in_mem_valid = Bool(INPUT)
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@ -150,20 +124,8 @@ class VLSITopIO extends TopIO {
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val out_mem_valid = Bool(OUTPUT)
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}
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class MemDessert extends Module {
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val io = new MemDesserIO(params(HTIFWidth))
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val x = Module(new MemDesser(params(HTIFWidth)))
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io.narrow <> x.io.narrow
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io.wide <> x.io.wide
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}
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class Top extends Module {
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//val vic = ICacheConfig(sets = 128, assoc = 1, tl = tl, as = as, btb = BTBConfig(as, 8))
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//val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
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val nTiles = params(NTiles)
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val io = new VLSITopIO
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class Top extends Module with TopLevelParameters {
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val io = new TopIO
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val resetSigs = Vec.fill(nTiles){Bool()}
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val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))))
|
||||
@ -181,20 +143,20 @@ class Top extends Module {
|
||||
il := hl.reset
|
||||
tile.io.host.id := UInt(i)
|
||||
tile.io.host.reset := Reg(next=Reg(next=hl.reset))
|
||||
tile.io.host.pcr_req <> Queue(hl.pcr_req, 1)
|
||||
hl.pcr_rep <> Queue(tile.io.host.pcr_rep, 1)
|
||||
hl.ipi_req <> Queue(tile.io.host.ipi_req, 1)
|
||||
tile.io.host.ipi_rep <> Queue(hl.ipi_rep, 1)
|
||||
tile.io.host.pcr_req <> Queue(hl.pcr_req)
|
||||
hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
|
||||
hl.ipi_req <> Queue(tile.io.host.ipi_req)
|
||||
tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
|
||||
hl.debug_stats_pcr := tile.io.host.debug_stats_pcr
|
||||
}
|
||||
|
||||
io.host <> uncore.io.host
|
||||
|
||||
uncore.io.mem_backup.resp.valid := io.in_mem_valid
|
||||
|
||||
io.out_mem_valid := uncore.io.mem_backup.req.valid
|
||||
uncore.io.mem_backup.req.ready := io.out_mem_ready
|
||||
|
||||
io.mem_backup_en <> uncore.io.mem_backup_en
|
||||
io.mem <> uncore.io.mem
|
||||
|
||||
if(params(UseBackupMemoryPort)) {
|
||||
uncore.io.mem_backup.resp.valid := io.in_mem_valid
|
||||
io.out_mem_valid := uncore.io.mem_backup.req.valid
|
||||
uncore.io.mem_backup.req.ready := io.out_mem_ready
|
||||
io.mem_backup_en <> uncore.io.mem_backup_en
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,82 +1,10 @@
|
||||
package referencechip
|
||||
|
||||
import Chisel._
|
||||
import uncore._
|
||||
import rocket._
|
||||
import DRAMModel._
|
||||
import DRAMModel.MemModelConstants._
|
||||
|
||||
class FPGAOuterMemorySystem extends Module {
|
||||
val io = new Bundle {
|
||||
val tiles = Vec.fill(params(NTiles)){new TileLinkIO}.flip
|
||||
val htif = (new TileLinkIO).flip
|
||||
val incoherent = Vec.fill(params(LNClients)){Bool()}.asInput
|
||||
val mem = new MemIO
|
||||
}
|
||||
|
||||
val master = Module(new L2CoherenceAgent(0), {case CacheName => "L2"})
|
||||
val net = Module(new ReferenceChipCrossbarNetwork)
|
||||
net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
|
||||
net.io.masters.head <> master.io.inner
|
||||
master.io.incoherent zip io.incoherent map { case (m, c) => m := c }
|
||||
|
||||
val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
|
||||
conv.io.uncached <> master.io.outer
|
||||
io.mem.req_cmd <> Queue(conv.io.mem.req_cmd, 2)
|
||||
io.mem.req_data <> Queue(conv.io.mem.req_data, params(TLDataBits)/params(MIFDataBits))
|
||||
conv.io.mem.resp <> Queue(io.mem.resp)
|
||||
}
|
||||
|
||||
class FPGAUncore extends Module {
|
||||
val (htifw, nTiles) = (params(HTIFWidth),params(NTiles))
|
||||
val io = new Bundle {
|
||||
val host = new HostIO(htifw)
|
||||
val mem = new MemIO
|
||||
val tiles = Vec.fill(nTiles){new TileLinkIO}.flip
|
||||
val htif = Vec.fill(nTiles){new HTIFIO}.flip
|
||||
val incoherent = Vec.fill(nTiles){Bool()}.asInput
|
||||
}
|
||||
val htif = Module(new HTIF(CSRs.reset))
|
||||
val outmemsys = Module(new FPGAOuterMemorySystem)
|
||||
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
|
||||
outmemsys.io.incoherent := incoherentWithHtif
|
||||
htif.io.cpu <> io.htif
|
||||
outmemsys.io.mem <> io.mem
|
||||
|
||||
// Add networking headers and endpoint queues
|
||||
(outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map {
|
||||
case ((outer, client), i) =>
|
||||
outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, false))
|
||||
outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, false))
|
||||
outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i, true))
|
||||
client.grant <> Queue(outer.grant, 1, pipe = true)
|
||||
client.probe <> Queue(outer.probe)
|
||||
}
|
||||
|
||||
htif.io.host.out <> io.host.out
|
||||
htif.io.host.in <> io.host.in
|
||||
}
|
||||
|
||||
class FPGATopIO extends TopIO
|
||||
|
||||
class FPGATop extends Module {
|
||||
/*
|
||||
val ntiles = 1
|
||||
val nmshrs = 2
|
||||
val htif_width = 16
|
||||
val co = new MESICoherence(new FullRepresentation(ntiles+1))
|
||||
implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, 1, ntiles+1)
|
||||
implicit val as = AddressSpaceConfiguration(params[Int]("PADDR_BITS"), params[Int]("VADDR_BITS"), params[Int]("PGIDX_BITS"), params[Int]("ASID_BITS"), params[Int]("PERM_BITS"))
|
||||
implicit val tl = TileLinkConfiguration(co = co, ln = ln,
|
||||
addrBits = as.paddrBits-params[Int]("OFFSET_BITS"),
|
||||
clientXactIdBits = log2Up(1+8),
|
||||
masterXactIdBits = 2*log2Up(2*1+1),
|
||||
dataBits = params[Int]("CACHE_DATA_SIZE_IN_BYTES")*8,
|
||||
writeMaskBits = params[Int]("WRITE_MASK_BITS"),
|
||||
wordAddrBits = params[Int]("SUBWORD_ADDR_BITS"),
|
||||
atomicOpBits = params[Int]("ATOMIC_OP_BITS"))
|
||||
implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 8)
|
||||
implicit val mif = MemoryIFConfiguration(params[Int]("MEM_ADDR_BITS"), params[Int]("MEM_DATA_BITS"), params[Int]("MEM_TAG_BITS"), params[Int]("MEM_DATA_BEATS"))
|
||||
implicit val uc = FPGAUncoreConfiguration(l2, tl, mif, ntiles, nSCR = 64, offsetBits = params[Int]("OFFSET_BITS"))
|
||||
|
||||
val ic = ICacheConfig(64, 1, ntlb = 4, tl = tl, as = as, btb = BTBConfig(as, 8, 2))
|
||||
@ -85,35 +13,6 @@ class FPGATop extends Module {
|
||||
fastMulDiv = false)
|
||||
*/
|
||||
|
||||
val nTiles = params(NTiles)
|
||||
val io = new FPGATopIO
|
||||
|
||||
val resetSigs = Vec.fill(nTiles){Bool()}
|
||||
val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))))
|
||||
val uncore = Module(new FPGAUncore)
|
||||
|
||||
for (i <- 0 until nTiles) {
|
||||
val hl = uncore.io.htif(i)
|
||||
val tl = uncore.io.tiles(i)
|
||||
val il = uncore.io.incoherent(i)
|
||||
|
||||
resetSigs(i) := hl.reset
|
||||
val tile = tileList(i)
|
||||
|
||||
tile.io.tilelink <> tl
|
||||
il := hl.reset
|
||||
tile.io.host.id := UInt(i)
|
||||
tile.io.host.reset := Reg(next=Reg(next=hl.reset))
|
||||
tile.io.host.pcr_req <> Queue(hl.pcr_req)
|
||||
hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
|
||||
hl.ipi_req <> Queue(tile.io.host.ipi_req)
|
||||
tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
|
||||
}
|
||||
|
||||
uncore.io.host <> io.host
|
||||
uncore.io.mem <> io.mem
|
||||
}
|
||||
|
||||
abstract class AXISlave extends Module {
|
||||
val aw = 5
|
||||
val dw = 32
|
||||
@ -126,7 +25,7 @@ abstract class AXISlave extends Module {
|
||||
|
||||
class Slave extends AXISlave
|
||||
{
|
||||
val top = Module(new FPGATop)
|
||||
val top = Module(new Top)
|
||||
|
||||
val memw = top.io.mem.resp.bits.data.getWidth
|
||||
val htifw = top.io.host.in.bits.getWidth
|
||||
|
||||
66
src/main/scala/vlsi.scala
Normal file
66
src/main/scala/vlsi.scala
Normal file
@ -0,0 +1,66 @@
|
||||
package referencechip
|
||||
|
||||
import Chisel._
|
||||
import uncore._
|
||||
|
||||
class MemDessert extends Module {
|
||||
val io = new MemDesserIO(params(HTIFWidth))
|
||||
val x = Module(new MemDesser(params(HTIFWidth)))
|
||||
io.narrow <> x.io.narrow
|
||||
io.wide <> x.io.wide
|
||||
}
|
||||
|
||||
object VLSIUtils {
|
||||
def doOuterMemorySystemSerdes(llc: MemPipeIO, mem: MemIO,
|
||||
backup: MemSerializedIO, en: Bool, w: Int) {
|
||||
val mem_serdes = Module(new MemSerdes(w))
|
||||
val wide = mem_serdes.io.wide
|
||||
llc.req_cmd.ready := Mux(en, wide.req_cmd.ready, mem.req_cmd.ready)
|
||||
mem.req_cmd.valid := llc.req_cmd.valid && !en
|
||||
mem.req_cmd.bits := llc.req_cmd.bits
|
||||
wide.req_cmd.valid := llc.req_cmd.valid && en
|
||||
wide.req_cmd.bits := llc.req_cmd.bits
|
||||
|
||||
llc.req_data.ready := Mux(en, wide.req_data.ready, mem.req_data.ready)
|
||||
mem.req_data.valid := llc.req_data.valid && !en
|
||||
mem.req_data.bits := llc.req_data.bits
|
||||
wide.req_data.valid := llc.req_data.valid && en
|
||||
wide.req_data.bits := llc.req_data.bits
|
||||
|
||||
llc.resp.valid := Mux(en, wide.resp.valid, mem.resp.valid)
|
||||
llc.resp.bits := Mux(en, wide.resp.bits, mem.resp.bits)
|
||||
mem.resp.ready := Bool(true)
|
||||
|
||||
backup <> mem_serdes.io.narrow
|
||||
}
|
||||
|
||||
def padOutHTIFWithDividedClock(htif: HTIFModuleIO, child: MemSerializedIO,
|
||||
parent: MemSerializedIO, host: HostIO,
|
||||
en: Bool, htifW: Int) {
|
||||
val hio = Module((new SlowIO(512)) { Bits(width = htifW+1) })
|
||||
hio.io.set_divisor.valid := htif.scr.wen && (htif.scr.waddr === UInt(63))
|
||||
hio.io.set_divisor.bits := htif.scr.wdata
|
||||
htif.scr.rdata(63) := hio.io.divisor
|
||||
|
||||
hio.io.out_fast.valid := htif.host.out.valid || child.req.valid
|
||||
hio.io.out_fast.bits := Cat(htif.host.out.valid, Mux(htif.host.out.valid, htif.host.out.bits, child.req.bits))
|
||||
htif.host.out.ready := hio.io.out_fast.ready
|
||||
child.req.ready := hio.io.out_fast.ready && !htif.host.out.valid
|
||||
host.out.valid := hio.io.out_slow.valid && hio.io.out_slow.bits(htifW)
|
||||
host.out.bits := hio.io.out_slow.bits
|
||||
parent.req.valid := hio.io.out_slow.valid && !hio.io.out_slow.bits(htifW)
|
||||
hio.io.out_slow.ready := Mux(hio.io.out_slow.bits(htifW), host.out.ready, parent.req.ready)
|
||||
|
||||
val mem_backup_resp_valid = en && parent.resp.valid
|
||||
hio.io.in_slow.valid := mem_backup_resp_valid || host.in.valid
|
||||
hio.io.in_slow.bits := Cat(mem_backup_resp_valid, host.in.bits)
|
||||
host.in.ready := hio.io.in_slow.ready
|
||||
child.resp.valid := hio.io.in_fast.valid && hio.io.in_fast.bits(htifW)
|
||||
child.resp.bits := hio.io.in_fast.bits
|
||||
htif.host.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htifW)
|
||||
htif.host.in.bits := hio.io.in_fast.bits
|
||||
hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htifW), Bool(true), htif.host.in.ready)
|
||||
host.clk := hio.io.clk_slow
|
||||
host.clk_edge := Reg(next=host.clk && !Reg(next=host.clk))
|
||||
}
|
||||
}
|
||||
2
uncore
2
uncore
@ -1 +1 @@
|
||||
Subproject commit 44f5112536350d37e7fe804ad9fe42c3516cb4c5
|
||||
Subproject commit d12f381645803a5c21bc0559494244ef6f2aad08
|
||||
Loading…
Reference in New Issue
Block a user