diff --git a/src/main/scala/PublicConfigs.scala b/src/main/scala/PublicConfigs.scala
index 7769576c..8fd57a18 100644
--- a/src/main/scala/PublicConfigs.scala
+++ b/src/main/scala/PublicConfigs.scala
@@ -11,6 +11,23 @@ class DefaultCPPConfig extends DefaultConfig
 class DefaultConfig extends ChiselConfig {
   val top:World.TopDefs = {
     (pname,site,here) => pname match {
+      //HTIF Parameters
+      case HTIFWidth => 16
+      case HTIFNSCR => 64
+      case HTIFOffsetBits => site(CacheBlockOffsetBits)
+      case HTIFNCores => site(NTiles)
+      //Memory Parameters
+      case PAddrBits => 32
+      case VAddrBits => 43
+      case PgIdxBits => 13
+      case ASIdBits => 7
+      case PermBits => 6
+      case PPNBits => site(PAddrBits) - site(PgIdxBits)
+      case VPNBits => site(VAddrBits) - site(PgIdxBits)
+      case MIFTagBits => 5
+      case MIFDataBits => 128
+      case MIFAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
+      case MIFDataBeats => site(TLDataBits)/site(MIFDataBits)
       //Params used by all caches
       case ECCCode => None
       case WordBits => site(XprLen)
@@ -21,12 +38,12 @@ class DefaultConfig extends ChiselConfig {
       }
       case NSets => site(CacheName) match {
         case "L1I" => 128
-        case "L1D" => 128
+        case "L1D" => Knob("L1D_SETS") //128
         case "L2" => 512 
       }
       case NWays => site(CacheName) match {
         case "L1I" => 2
-        case "L1D" => 4
+        case "L1D" => Knob("L1D_WAYS") //4
         case "L2" => 8
       }
       case RowBits => site(CacheName) match {
@@ -42,11 +59,11 @@ class DefaultConfig extends ChiselConfig {
       case NDTLBEntries => 8
       case StoreDataQueueDepth => 17
       case ReplayQueueDepth => 16
-      case NMSHRs => site[Int]("NMSHRS")
+      case NMSHRs => Knob("L1D_MSHRS")
       case LRSCCycles => 32 
       //L2CacheParams
-      case NReleaseTransactors => site[Int]("NL2_REL_XACTS")
-      case NAcquireTransactors => site[Int]("NL2_ACQ_XACTS")
+      case NReleaseTransactors => Knob("L2_REL_XACTS")
+      case NAcquireTransactors => Knob("L2_ACQ_XACTS")
       case NClients => site(NTiles) + 1
       //Tile Constants
       case BuildRoCC => None
@@ -67,23 +84,6 @@ class DefaultConfig extends ChiselConfig {
       case CoreInstBits => 32
       case CoreDataBits => site(XprLen)
       case CoreDCacheReqTagBits => 7 + log2Up(here(NDCachePorts))
-      //HTIF Parameters
-      case HTIFWidth => 16
-      case HTIFNSCR => 64
-      case HTIFOffsetBits => site(CacheBlockOffsetBits)
-      case HTIFNCores => site(NTiles)
-      //Memory Parameters
-      case PAddrBits => 32
-      case VAddrBits => 43
-      case PgIdxBits => 13
-      case ASIdBits => 7
-      case PermBits => 6
-      case PPNBits => site(PAddrBits) - site(PgIdxBits)
-      case VPNBits => site(VAddrBits) - site(PgIdxBits)
-      case MIFTagBits => 5
-      case MIFDataBits => 128
-      case MIFAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
-      case MIFDataBeats => 4
       //Uncore Paramters
       case LNMasters => site(NBanks)
       case LNClients => site(NTiles)+1
@@ -96,13 +96,13 @@ class DefaultConfig extends ChiselConfig {
       case TLWriteMaskBits => 6
       case TLWordAddrBits  => 3
       case TLAtomicOpBits  => 4
-      case NTiles => here[Int]("NTILES")
-      case NBanks => here[Int]("NBANKS")
+      case NTiles => Knob("NTILES")
+      case NBanks => Knob("NBANKS")
       case BankIdLSB => 5
       case CacheBlockBytes => 64
       case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
-      case BuildDRAMSideLLC => () => {
-        val refill = site(TLDataBits)/site(MIFDataBits)
+      case UseBackupMemoryPort => true
+      case BuildDRAMSideLLC => (refill: Int) => {
         if(site[Boolean]("USE_DRAMSIDE_LLC")) {
           val tag = Mem(Bits(width = 152), 512, seqRead = true)
           val data = Mem(Bits(width = 64), 4096, seqRead = true)
@@ -110,11 +110,11 @@ class DefaultConfig extends ChiselConfig {
             refill_cycles=refill, tagLeaf=tag, dataLeaf=data))
         } else { Module(new DRAMSideLLCNull(16, refill)) }
       }
-      case BuildCoherentMaster => (id: Int) => {
-        if(!site[Boolean]("USE_DRAMSIDE_LLC")) { 
-          Module(new L2CoherenceAgent(id), { case CacheName => "L2" })
-        } else {
+      case BuildCoherenceMaster => (id: Int) => {
+        if(site[Boolean]("USE_L2_CACHE")) { 
           Module(new L2HellaCache(id), { case CacheName => "L2" })
+        } else {
+          Module(new L2CoherenceAgent(id), { case CacheName => "L2" })
         }
       }
       case Coherence => {
@@ -129,17 +129,20 @@ class DefaultConfig extends ChiselConfig {
           else new MICoherence(dir)
         }
       }
-      //DesignSpaceConstants  //TODO KNOBS
-      case "NTILES" => 1
-      case "NBANKS" => 1
-      case "HTIF_WIDTH" => 16
       case "ENABLE_SHARING" => true
       case "ENABLE_CLEAN_EXCLUSIVE" => true
       case "USE_DRAMSIDE_LLC" => true
-      case "NL2_REL_XACTS" => 1
-      case "NL2_ACQ_XACTS" => 7
-      case "NMSHRS" => 2
+      case "USE_L2_CACHE" => false 
     }
   }
+  override val knobVal:Any=>Any = {
+    case "NTILES" => 1
+    case "NBANKS" => 1
+    case "L2_REL_XACTS" => 1
+    case "L2_ACQ_XACTS" => 7
+    case "L1D_MSHRS" => 2
+    case "L1D_SETS" => 128
+    case "L1D_WAYS" => 4
+  }
 }
 
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 505ee52d..3a393126 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -10,12 +10,19 @@ case object NBanks extends Field[Int]
 case object BankIdLSB extends Field[Int]
 case object CacheBlockBytes extends Field[Int]
 case object CacheBlockOffsetBits extends Field[Int]
-case object BuildDRAMSideLLC extends Field[() => DRAMSideLLCLike]
-case object BuildCoherentMaster extends Field[(Int) => CoherenceAgent]
+case object BuildDRAMSideLLC extends Field[(Int) => DRAMSideLLCLike]
+case object BuildCoherenceMaster extends Field[(Int) => CoherenceAgent]
+case object UseBackupMemoryPort extends Field[Boolean]
 case object Coherence extends Field[CoherencePolicyWithUncached]
 
-class OuterMemorySystem extends Module
-{
+abstract trait TopLevelParameters extends UsesParameters {
+  val htifW = params(HTIFWidth)
+  val nTiles = params(NTiles)
+  val nBanks = params(NBanks)
+  val lsb = params(BankIdLSB)
+  val refillCycles = params(MIFDataBeats)
+}
+class OuterMemorySystem extends Module with TopLevelParameters {
   val io = new Bundle {
     val tiles = Vec.fill(params(NTiles)){new TileLinkIO}.flip
     val htif = (new TileLinkIO).flip
@@ -25,15 +32,14 @@ class OuterMemorySystem extends Module
     val mem_backup_en = Bool(INPUT)
   }
 
-  val refill_cycles = params(TLDataBits)/params(MIFDataBits)
-  val llc = params(BuildDRAMSideLLC)()
-  val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherentMaster))
-
+  // Create a simple NoC and points of coherence serialization
   val net = Module(new ReferenceChipCrossbarNetwork)
+  val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherenceMaster))
   net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
   net.io.masters zip (masterEndpoints.map(_.io.inner)) map { case (net, end) => net <> end }
   masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
 
+  // Create a converter between TileLinkIO and MemIO
   val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
   if(params(NBanks) > 1) {
     val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(params(NBanks)))
@@ -42,107 +48,75 @@ class OuterMemorySystem extends Module
   } else {
     conv.io.uncached <> masterEndpoints.head.io.outer
   }
-  llc.io.cpu.req_cmd <> Queue(conv.io.mem.req_cmd)
-  llc.io.cpu.req_data <> Queue(conv.io.mem.req_data, refill_cycles)
+
+  // Create a DRAM-side LLC
+  val llc = params(BuildDRAMSideLLC)(refillCycles)
+  llc.io.cpu.req_cmd <> Queue(conv.io.mem.req_cmd, 2)
+  llc.io.cpu.req_data <> Queue(conv.io.mem.req_data, refillCycles)
   conv.io.mem.resp <> llc.io.cpu.resp
-
-  // mux between main and backup memory ports
-  val mem_serdes = Module(new MemSerdes(params(HTIFWidth)))
-  val mem_cmdq = Module(new Queue(new MemReqCmd, 2))
-  mem_cmdq.io.enq <> llc.io.mem.req_cmd
-  mem_cmdq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_cmd.ready, io.mem.req_cmd.ready)
-  io.mem.req_cmd.valid := mem_cmdq.io.deq.valid && !io.mem_backup_en
-  io.mem.req_cmd.bits := mem_cmdq.io.deq.bits
-  mem_serdes.io.wide.req_cmd.valid := mem_cmdq.io.deq.valid && io.mem_backup_en
-  mem_serdes.io.wide.req_cmd.bits := mem_cmdq.io.deq.bits
-
-  val mem_dataq = Module(new Queue(new MemData, refill_cycles))
-  mem_dataq.io.enq <> llc.io.mem.req_data
-  mem_dataq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_data.ready, io.mem.req_data.ready)
-  io.mem.req_data.valid := mem_dataq.io.deq.valid && !io.mem_backup_en
-  io.mem.req_data.bits := mem_dataq.io.deq.bits
-  mem_serdes.io.wide.req_data.valid := mem_dataq.io.deq.valid && io.mem_backup_en
-  mem_serdes.io.wide.req_data.bits := mem_dataq.io.deq.bits
-
-  llc.io.mem.resp.valid := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.valid, io.mem.resp.valid)
-  io.mem.resp.ready := Bool(true)
-  llc.io.mem.resp.bits := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.bits, io.mem.resp.bits)
-
-  io.mem_backup <> mem_serdes.io.narrow
+  
+  // Create a SerDes for backup memory port
+  if(params(UseBackupMemoryPort)) {
+    VLSIUtils.doOuterMemorySystemSerdes(llc.io.mem, io.mem, io.mem_backup,
+                                        io.mem_backup_en, params(HTIFWidth))
+  } else {
+    io.mem <> llc.io.mem 
+  }
 }
 
-
-class Uncore extends Module
-{
-  require(params(BankIdLSB) + log2Up(params(NBanks)) < params(MIFAddrBits))
-  val htif_width = params(HTIFWidth)
+class Uncore extends Module with TopLevelParameters {
   val io = new Bundle {
-    val host = new HostIO(htif_width)
+    val host = new HostIO
     val mem = new MemIO
-    val tiles = Vec.fill(params(NTiles)){new TileLinkIO}.flip
-    val htif = Vec.fill(params(NTiles)){new HTIFIO}.flip
-    val incoherent = Vec.fill(params(NTiles)){Bool()}.asInput
-    val mem_backup = new MemSerializedIO(htif_width)
+    val tiles = Vec.fill(nTiles){new TileLinkIO}.flip
+    val htif = Vec.fill(nTiles){new HTIFIO}.flip
+    val incoherent = Vec.fill(nTiles){Bool()}.asInput
+    val mem_backup = new MemSerializedIO(htifW)
     val mem_backup_en = Bool(INPUT)
   }
-  val htif = Module(new HTIF(CSRs.reset))
-  val outmemsys = Module(new OuterMemorySystem)
-  val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
-  outmemsys.io.incoherent := incoherentWithHtif
-  htif.io.cpu <> io.htif
-  outmemsys.io.mem <> io.mem
-  outmemsys.io.mem_backup_en <> io.mem_backup_en
 
-  // Add networking headers and endpoint queues
-  def convertAddrToBank(addr: Bits): UInt = {
-    addr(params(BankIdLSB) + log2Up(params(NBanks)) - 1, params(BankIdLSB))
+  // Used to hash physical addresses to banks
+  require(params(BankIdLSB) + log2Up(params(NBanks)) < params(MIFAddrBits))
+  def addrToBank(addr: Bits): UInt = {
+    if(nBanks > 1) addr( lsb + log2Up(nBanks) - 1, lsb)
+    else UInt(0)
   }
 
-  (outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map { 
-    case ((outer, client), i) => 
-      outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, params(NBanks), convertAddrToBank _))
-      outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, params(NBanks), convertAddrToBank _))
+  val htif = Module(new HTIF(CSRs.reset)) // One HTIF module per chip
+  val outmemsys = Module(new OuterMemorySystem) // NoC, LLC and SerDes
+
+  // Wire outer mem system to tiles and htif, adding
+  //   networking headers and endpoint queues
+  (outmemsys.io.tiles :+ outmemsys.io.htif) // Collect outward-facing TileLink ports
+    .zip(io.tiles :+ htif.io.mem)           // Zip them with matching ports from clients
+    .zipWithIndex                           // Index them
+    .map { case ((outer, client), i) =>     // Then use the index and bank hash to
+                                            //   overwrite the networking header
+      outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, nBanks, addrToBank _))
+      outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, nBanks, addrToBank _))
       outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i, true))
       client.grant <> Queue(outer.grant, 1, pipe = true)
       client.probe <> Queue(outer.probe)
-  }
-
-  // pad out the HTIF using a divided clock
-  val hio = Module((new SlowIO(512)) { Bits(width = params(HTIFWidth)+1) })
-  hio.io.set_divisor.valid := htif.io.scr.wen && htif.io.scr.waddr === 63
-  hio.io.set_divisor.bits := htif.io.scr.wdata
-  htif.io.scr.rdata(63) := hio.io.divisor
-
-  hio.io.out_fast.valid := htif.io.host.out.valid || outmemsys.io.mem_backup.req.valid
-  hio.io.out_fast.bits := Cat(htif.io.host.out.valid, Mux(htif.io.host.out.valid, htif.io.host.out.bits, outmemsys.io.mem_backup.req.bits))
-  htif.io.host.out.ready := hio.io.out_fast.ready
-  outmemsys.io.mem_backup.req.ready := hio.io.out_fast.ready && !htif.io.host.out.valid
-  io.host.out.valid := hio.io.out_slow.valid && hio.io.out_slow.bits(htif_width)
-  io.host.out.bits := hio.io.out_slow.bits
-  io.mem_backup.req.valid := hio.io.out_slow.valid && !hio.io.out_slow.bits(htif_width)
-  hio.io.out_slow.ready := Mux(hio.io.out_slow.bits(htif_width), io.host.out.ready, io.mem_backup.req.ready)
-
-  val mem_backup_resp_valid = io.mem_backup_en && io.mem_backup.resp.valid
-  hio.io.in_slow.valid := mem_backup_resp_valid || io.host.in.valid
-  hio.io.in_slow.bits := Cat(mem_backup_resp_valid, io.host.in.bits)
-  io.host.in.ready := hio.io.in_slow.ready
-  outmemsys.io.mem_backup.resp.valid := hio.io.in_fast.valid && hio.io.in_fast.bits(htif_width)
-  outmemsys.io.mem_backup.resp.bits := hio.io.in_fast.bits
-  htif.io.host.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htif_width)
-  htif.io.host.in.bits := hio.io.in_fast.bits
-  hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htif_width), Bool(true), htif.io.host.in.ready)
-  io.host.clk := hio.io.clk_slow
-  io.host.clk_edge := Reg(next=io.host.clk && !Reg(next=io.host.clk))
+    } 
+  outmemsys.io.incoherent := (io.incoherent :+ Bool(true).asInput)
 
+  // Wire the htif to the memory port(s) and host interface
   io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr
+  htif.io.cpu <> io.htif
+  outmemsys.io.mem <> io.mem
+  if(params(UseBackupMemoryPort)) {
+    outmemsys.io.mem_backup_en := io.mem_backup_en
+    VLSIUtils.padOutHTIFWithDividedClock(htif.io, outmemsys.io.mem_backup, 
+      io.mem_backup, io.host, io.mem_backup_en, htifW)
+  } else {
+    htif.io.host.out <> io.host.out
+    htif.io.host.in <> io.host.in
+  }
 }
 
-class TopIO extends Bundle  {
-  val host    = new HostIO(params(HTIFWidth))
+class TopIO extends Bundle {
+  val host    = new HostIO
   val mem     = new MemIO
-}
-
-class VLSITopIO extends TopIO {
   val mem_backup_en = Bool(INPUT)
   val in_mem_ready = Bool(OUTPUT)
   val in_mem_valid = Bool(INPUT)
@@ -150,20 +124,8 @@ class VLSITopIO extends TopIO {
   val out_mem_valid = Bool(OUTPUT)
 }
 
-class MemDessert extends Module {
-  val io = new MemDesserIO(params(HTIFWidth))
-  val x = Module(new MemDesser(params(HTIFWidth)))
-  io.narrow <> x.io.narrow
-  io.wide <> x.io.wide
-}
-
-class Top extends Module {
-
-  //val vic = ICacheConfig(sets = 128, assoc = 1, tl = tl, as = as, btb = BTBConfig(as, 8))
-  //val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
-
-  val nTiles = params(NTiles)
-  val io = new VLSITopIO
+class Top extends Module with TopLevelParameters {
+  val io = new TopIO
 
   val resetSigs = Vec.fill(nTiles){Bool()}
   val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))))
@@ -181,20 +143,20 @@ class Top extends Module {
     il := hl.reset
     tile.io.host.id := UInt(i)
     tile.io.host.reset := Reg(next=Reg(next=hl.reset))
-    tile.io.host.pcr_req <> Queue(hl.pcr_req, 1)
-    hl.pcr_rep <> Queue(tile.io.host.pcr_rep, 1)
-    hl.ipi_req <> Queue(tile.io.host.ipi_req, 1)
-    tile.io.host.ipi_rep <> Queue(hl.ipi_rep, 1)
+    tile.io.host.pcr_req <> Queue(hl.pcr_req)
+    hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
+    hl.ipi_req <> Queue(tile.io.host.ipi_req)
+    tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
     hl.debug_stats_pcr := tile.io.host.debug_stats_pcr
   }
 
   io.host <> uncore.io.host
-
-  uncore.io.mem_backup.resp.valid := io.in_mem_valid
-
-  io.out_mem_valid := uncore.io.mem_backup.req.valid
-  uncore.io.mem_backup.req.ready := io.out_mem_ready
-
-  io.mem_backup_en <> uncore.io.mem_backup_en
   io.mem <> uncore.io.mem
+
+  if(params(UseBackupMemoryPort)) {
+    uncore.io.mem_backup.resp.valid := io.in_mem_valid
+    io.out_mem_valid := uncore.io.mem_backup.req.valid
+    uncore.io.mem_backup.req.ready := io.out_mem_ready
+    io.mem_backup_en <> uncore.io.mem_backup_en
+  }
 }
diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala
index 50184a0b..95290b46 100644
--- a/src/main/scala/fpga.scala
+++ b/src/main/scala/fpga.scala
@@ -1,82 +1,10 @@
 package referencechip
 
 import Chisel._
-import uncore._
-import rocket._
-import DRAMModel._
-import DRAMModel.MemModelConstants._
 
-class FPGAOuterMemorySystem extends Module {
-  val io = new Bundle {
-    val tiles = Vec.fill(params(NTiles)){new TileLinkIO}.flip
-    val htif = (new TileLinkIO).flip
-    val incoherent = Vec.fill(params(LNClients)){Bool()}.asInput
-    val mem = new MemIO
-  }
-
-  val master = Module(new L2CoherenceAgent(0), {case CacheName => "L2"})
-  val net = Module(new ReferenceChipCrossbarNetwork)
-  net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
-  net.io.masters.head <> master.io.inner
-  master.io.incoherent zip io.incoherent map { case (m, c) => m := c }
-
-  val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
-  conv.io.uncached <> master.io.outer
-  io.mem.req_cmd <> Queue(conv.io.mem.req_cmd, 2)
-  io.mem.req_data <> Queue(conv.io.mem.req_data, params(TLDataBits)/params(MIFDataBits))
-  conv.io.mem.resp <> Queue(io.mem.resp)
-}
-
-class FPGAUncore extends Module {
-  val (htifw, nTiles) = (params(HTIFWidth),params(NTiles))
-  val io = new Bundle {
-    val host = new HostIO(htifw)
-    val mem = new MemIO
-    val tiles = Vec.fill(nTiles){new TileLinkIO}.flip
-    val htif = Vec.fill(nTiles){new HTIFIO}.flip
-    val incoherent = Vec.fill(nTiles){Bool()}.asInput
-  }
-  val htif = Module(new HTIF(CSRs.reset))
-  val outmemsys = Module(new FPGAOuterMemorySystem)
-  val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
-  outmemsys.io.incoherent := incoherentWithHtif
-  htif.io.cpu <> io.htif
-  outmemsys.io.mem <> io.mem
-
-  // Add networking headers and endpoint queues
-  (outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map { 
-    case ((outer, client), i) => 
-      outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, false))
-      outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, false))
-      outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i, true))
-      client.grant <> Queue(outer.grant, 1, pipe = true)
-      client.probe <> Queue(outer.probe)
-  }
-
-  htif.io.host.out <> io.host.out
-  htif.io.host.in <> io.host.in
-}
-
-class FPGATopIO extends TopIO
-
-class FPGATop extends Module {
   /*
   val ntiles = 1
   val nmshrs = 2
-  val htif_width = 16
-  val co = new MESICoherence(new FullRepresentation(ntiles+1))
-  implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, 1, ntiles+1)
-  implicit val as = AddressSpaceConfiguration(params[Int]("PADDR_BITS"), params[Int]("VADDR_BITS"), params[Int]("PGIDX_BITS"), params[Int]("ASID_BITS"), params[Int]("PERM_BITS"))
-  implicit val tl = TileLinkConfiguration(co = co, ln = ln,
-                                          addrBits = as.paddrBits-params[Int]("OFFSET_BITS"), 
-                                          clientXactIdBits = log2Up(1+8), 
-                                          masterXactIdBits = 2*log2Up(2*1+1), 
-                                          dataBits = params[Int]("CACHE_DATA_SIZE_IN_BYTES")*8, 
-                                          writeMaskBits = params[Int]("WRITE_MASK_BITS"), 
-                                          wordAddrBits = params[Int]("SUBWORD_ADDR_BITS"), 
-                                          atomicOpBits = params[Int]("ATOMIC_OP_BITS"))
-  implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 8)
-  implicit val mif = MemoryIFConfiguration(params[Int]("MEM_ADDR_BITS"), params[Int]("MEM_DATA_BITS"), params[Int]("MEM_TAG_BITS"), params[Int]("MEM_DATA_BEATS"))
   implicit val uc = FPGAUncoreConfiguration(l2, tl, mif, ntiles, nSCR = 64, offsetBits = params[Int]("OFFSET_BITS"))
 
   val ic = ICacheConfig(64, 1, ntlb = 4, tl = tl, as = as, btb = BTBConfig(as, 8, 2))
@@ -85,35 +13,6 @@ class FPGATop extends Module {
                                fastMulDiv = false)
 */
 
-  val nTiles = params(NTiles)
-  val io = new FPGATopIO
- 
-  val resetSigs = Vec.fill(nTiles){Bool()}
-  val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))))
-  val uncore = Module(new FPGAUncore)
-
-  for (i <- 0 until nTiles) {
-    val hl = uncore.io.htif(i)
-    val tl = uncore.io.tiles(i)
-    val il = uncore.io.incoherent(i)
-
-    resetSigs(i) := hl.reset
-    val tile = tileList(i)
-
-    tile.io.tilelink <> tl
-    il := hl.reset
-    tile.io.host.id := UInt(i)
-    tile.io.host.reset := Reg(next=Reg(next=hl.reset))
-    tile.io.host.pcr_req <> Queue(hl.pcr_req)
-    hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
-    hl.ipi_req <> Queue(tile.io.host.ipi_req)
-    tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
-  }
- 
-  uncore.io.host <> io.host
-  uncore.io.mem <> io.mem
-}
-
 abstract class AXISlave extends Module {
   val aw = 5
   val dw = 32
@@ -126,7 +25,7 @@ abstract class AXISlave extends Module {
 
 class Slave extends AXISlave
 {
-  val top = Module(new FPGATop)
+  val top = Module(new Top)
 
   val memw = top.io.mem.resp.bits.data.getWidth
   val htifw = top.io.host.in.bits.getWidth
diff --git a/src/main/scala/vlsi.scala b/src/main/scala/vlsi.scala
new file mode 100644
index 00000000..b5facb31
--- /dev/null
+++ b/src/main/scala/vlsi.scala
@@ -0,0 +1,66 @@
+package referencechip
+
+import Chisel._
+import uncore._
+
+class MemDessert extends Module {
+  val io = new MemDesserIO(params(HTIFWidth))
+  val x = Module(new MemDesser(params(HTIFWidth)))
+  io.narrow <> x.io.narrow
+  io.wide <> x.io.wide
+}
+
+object VLSIUtils {
+  def doOuterMemorySystemSerdes(llc: MemPipeIO, mem: MemIO, 
+      backup: MemSerializedIO, en: Bool, w: Int) {
+    val mem_serdes = Module(new MemSerdes(w))
+    val wide = mem_serdes.io.wide
+    llc.req_cmd.ready := Mux(en, wide.req_cmd.ready, mem.req_cmd.ready)
+    mem.req_cmd.valid := llc.req_cmd.valid && !en
+    mem.req_cmd.bits := llc.req_cmd.bits
+    wide.req_cmd.valid := llc.req_cmd.valid && en
+    wide.req_cmd.bits := llc.req_cmd.bits
+
+    llc.req_data.ready := Mux(en, wide.req_data.ready, mem.req_data.ready)
+    mem.req_data.valid := llc.req_data.valid && !en
+    mem.req_data.bits := llc.req_data.bits
+    wide.req_data.valid := llc.req_data.valid && en
+    wide.req_data.bits := llc.req_data.bits
+
+    llc.resp.valid := Mux(en, wide.resp.valid, mem.resp.valid)
+    llc.resp.bits := Mux(en, wide.resp.bits, mem.resp.bits)
+    mem.resp.ready := Bool(true)
+
+    backup <> mem_serdes.io.narrow
+  }
+
+  def padOutHTIFWithDividedClock(htif: HTIFModuleIO, child: MemSerializedIO, 
+                      parent: MemSerializedIO, host: HostIO,
+                      en: Bool, htifW: Int) {
+    val hio = Module((new SlowIO(512)) { Bits(width = htifW+1) })
+    hio.io.set_divisor.valid := htif.scr.wen && (htif.scr.waddr === UInt(63))
+    hio.io.set_divisor.bits := htif.scr.wdata
+    htif.scr.rdata(63) := hio.io.divisor
+
+    hio.io.out_fast.valid := htif.host.out.valid || child.req.valid
+    hio.io.out_fast.bits := Cat(htif.host.out.valid, Mux(htif.host.out.valid, htif.host.out.bits, child.req.bits))
+    htif.host.out.ready := hio.io.out_fast.ready
+    child.req.ready := hio.io.out_fast.ready && !htif.host.out.valid
+    host.out.valid := hio.io.out_slow.valid && hio.io.out_slow.bits(htifW)
+    host.out.bits := hio.io.out_slow.bits
+    parent.req.valid := hio.io.out_slow.valid && !hio.io.out_slow.bits(htifW)
+    hio.io.out_slow.ready := Mux(hio.io.out_slow.bits(htifW), host.out.ready, parent.req.ready)
+
+    val mem_backup_resp_valid = en && parent.resp.valid
+    hio.io.in_slow.valid := mem_backup_resp_valid || host.in.valid
+    hio.io.in_slow.bits := Cat(mem_backup_resp_valid, host.in.bits)
+    host.in.ready := hio.io.in_slow.ready
+    child.resp.valid := hio.io.in_fast.valid && hio.io.in_fast.bits(htifW)
+    child.resp.bits := hio.io.in_fast.bits
+    htif.host.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htifW)
+    htif.host.in.bits := hio.io.in_fast.bits
+    hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htifW), Bool(true), htif.host.in.ready)
+    host.clk := hio.io.clk_slow
+    host.clk_edge := Reg(next=host.clk && !Reg(next=host.clk))
+  }
+}
diff --git a/uncore b/uncore
index 44f51125..d12f3816 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 44f5112536350d37e7fe804ad9fe42c3516cb4c5
+Subproject commit d12f381645803a5c21bc0559494244ef6f2aad08