riscv/rocket-chip
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Fix stupid D$ probe bug

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This commit is contained in:
Andrew Waterman 2017-07-06 00:26:32 -07:00
parent 90a7d6a343
commit be4eceec0d
1 changed files with 3 additions and 2 deletions
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5
src/main/scala/rocket/DCache.scala
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@ -474,7 +474,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
probe_bits.address := Cat(s2_victim_tag, s2_req.addr(idxMSB, idxLSB)) << idxLSB probe_bits.address := Cat(s2_victim_tag, s2_req.addr(idxMSB, idxLSB)) << idxLSB
} }
when (s2_probe) { when (s2_probe) {
s1_nack := true val probeNack = Wire(init = true.B)
when (s2_meta_error) { when (s2_meta_error) {
release_state := s_probe_retry release_state := s_probe_retry
}.elsewhen (s2_prb_ack_data) { }.elsewhen (s2_prb_ack_data) {
@ -485,9 +485,10 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
release_state := Mux(releaseDone, s_probe_write_meta, s_probe_rep_clean) release_state := Mux(releaseDone, s_probe_write_meta, s_probe_rep_clean)
}.otherwise { }.otherwise {
tl_out.c.valid := true tl_out.c.valid := true
s1_nack := !releaseDone probeNack := !releaseDone
release_state := Mux(releaseDone, s_ready, s_probe_rep_miss) release_state := Mux(releaseDone, s_ready, s_probe_rep_miss)
} }
when (probeNack) { s1_nack := true }
} }
when (release_state === s_probe_retry) { when (release_state === s_probe_retry) {
metaArb.io.in(6).valid := true metaArb.io.in(6).valid := true