From be4eceec0d911c485db0fedf8104fd10fe7a11d4 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 6 Jul 2017 00:26:32 -0700
Subject: [PATCH] Fix stupid D$ probe bug

---
 src/main/scala/rocket/DCache.scala | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala
index 98e89a9f..8717774e 100644
--- a/src/main/scala/rocket/DCache.scala
+++ b/src/main/scala/rocket/DCache.scala
@@ -474,7 +474,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
     probe_bits.address := Cat(s2_victim_tag, s2_req.addr(idxMSB, idxLSB)) << idxLSB
   }
   when (s2_probe) {
-    s1_nack := true
+    val probeNack = Wire(init = true.B)
     when (s2_meta_error) {
       release_state := s_probe_retry
     }.elsewhen (s2_prb_ack_data) {
@@ -485,9 +485,10 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
       release_state := Mux(releaseDone, s_probe_write_meta, s_probe_rep_clean)
     }.otherwise {
       tl_out.c.valid := true
-      s1_nack := !releaseDone
+      probeNack := !releaseDone
       release_state := Mux(releaseDone, s_ready, s_probe_rep_miss)
     }
+    when (probeNack) { s1_nack := true }
   }
   when (release_state === s_probe_retry) {
     metaArb.io.in(6).valid := true