add dummy mul_rdy signal
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parent
96c78829b4
commit
bcceb08373
@ -56,6 +56,7 @@ class ioCtrlDpath extends Bundle()
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val br_ltu = Bool('input);
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val div_rdy = Bool('input);
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val div_result_val = Bool('input);
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val mul_rdy = Bool('input);
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val mul_result_val = Bool('input);
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val ex_waddr = UFix(5,'input); // write addr from execute stage
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val mem_waddr = UFix(5,'input); // write addr from memory stage
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@ -628,6 +629,7 @@ class rocketCtrl extends Component
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((id_sync === SYNC_D) || (id_sync === SYNC_I)) && !io.dmem.req_rdy ||
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id_console_out_val && !io.console.rdy ||
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id_div_val.toBool && !io.dpath.div_rdy ||
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id_mul_val.toBool && !io.dpath.mul_rdy ||
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io.dpath.div_result_val ||
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io.dpath.mul_result_val
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);
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@ -289,6 +289,7 @@ class rocketDpath extends Component
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mul.io.in0 := ex_reg_rs1;
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mul.io.in1 := ex_reg_rs2;
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io.ctrl.mul_rdy := mul.io.mul_rdy
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io.ctrl.mul_result_val := mul.io.result_val;
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io.ctrl.ex_waddr := ex_reg_waddr; // for load/use hazard detection & bypass control
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@ -7,6 +7,7 @@ import Constants._;
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class ioMultiplier(width: Int) extends Bundle {
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// requests
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val mul_val = Bool('input);
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val mul_rdy = Bool('output);
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val dw = UFix(1, 'input);
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val mul_fn = UFix(2, 'input);
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val mul_tag = UFix(5, 'input);
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@ -61,6 +62,7 @@ class rocketMultiplier extends Component {
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val r_result_tag = Reg(Reg(Reg(r_tag)));
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val r_result_val = Reg(Reg(Reg(r_val)));
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io.mul_rdy := Bool(true)
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io.result := r_result;
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io.result_tag := r_result_tag;
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io.result_val := r_result_val;
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