riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

add dummy mul_rdy signal

Browse Source
This commit is contained in:
Andrew Waterman
2011-12-17 07:30:47 -08:00
parent 96c78829b4
commit bcceb08373
3 changed files with 7 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/ctrl.scala
View File

@ -56,6 +56,7 @@ class ioCtrlDpath extends Bundle()
val br_ltu = Bool('input);
val div_rdy = Bool('input);
val div_result_val = Bool('input);
val mul_rdy = Bool('input);
val mul_result_val = Bool('input);
val ex_waddr = UFix(5,'input); // write addr from execute stage
val mem_waddr = UFix(5,'input); // write addr from memory stage
@ -628,6 +629,7 @@ class rocketCtrl extends Component
((id_sync === SYNC_D) || (id_sync === SYNC_I)) && !io.dmem.req_rdy ||
id_console_out_val && !io.console.rdy ||
id_div_val.toBool && !io.dpath.div_rdy ||
id_mul_val.toBool && !io.dpath.mul_rdy ||
io.dpath.div_result_val ||
io.dpath.mul_result_val
);