riscv/rocket-chip
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bugfixes due to new hcl jar file

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This commit is contained in:
Rimas Avizienis 2011-11-30 21:54:55 -08:00
parent 11f0e3daf4
commit bc44572d99
3 changed files with 13 additions and 16 deletions
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11
rocket/src/main/scala/dpath.scala
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@ -45,7 +45,7 @@ class rocketDpath extends Component
val alu = new rocketDpathALU();
val ex_alu_out = alu.io.out;
val ex_jr_target = ex_alu_out(VADDR_BITS,0);
val ex_jr_target = ex_alu_out(VADDR_BITS-1,0);
val div = new rocketDivider(64);
val div_result = div.io.div_result_bits;
@ -60,7 +60,7 @@ class rocketDpath extends Component
val rfile = new rocketDpathRegfile();
// instruction fetch definitions
val if_reg_pc = Reg(resetVal = UFix(0,VADDR_BITS));
val if_reg_pc = Reg(resetVal = UFix(START_ADDR,VADDR_BITS));
// instruction decode definitions
val id_reg_valid = Reg(resetVal = Bool(false));
@ -141,15 +141,12 @@ class rocketDpath extends Component
Mux(io.ctrl.sel_pc === PC_BR, ex_branch_target,
Mux(io.ctrl.sel_pc === PC_J, ex_branch_target,
Mux(io.ctrl.sel_pc === PC_JR, ex_jr_target.toUFix,
Mux(io.ctrl.sel_pc === PC_PCR, mem_reg_wdata, // only used for ERET
Mux(io.ctrl.sel_pc === PC_PCR, mem_reg_wdata(VADDR_BITS-1,0), // only used for ERET
Mux(io.ctrl.sel_pc === PC_EVEC, pcr.io.evec,
Mux(io.ctrl.sel_pc === PC_MEM, mem_reg_pc,
UFix(0, VADDR_BITS)))))))))));
when (!io.host.start){
if_reg_pc <== UFix(START_ADDR, VADDR_BITS);
}
when (!io.ctrl.stallf) {
when (!io.ctrl.stallf && io.host.start) {
if_reg_pc <== if_next_pc.toUFix;
}

12
rocket/src/main/scala/icache_prefetch.scala
View File

@ -40,23 +40,23 @@ class rocketIPrefetcher extends Component() {
val ip_mem_resp_val = io.mem.resp_val && io.mem.resp_tag(0).toBool;
io.mem.req_val := io.icache.req_val & ~hit | (state === s_req_wait);
io.mem.req_tag := !(io.icache.req_val && !hit);
io.mem.req_addr := Mux(io.mem.req_tag.toBool, prefetch_addr, io.icache.req_addr);
io.mem.req_tag := Cat(Bits(0,2), !(io.icache.req_val && !hit));
io.mem.req_addr := Mux(io.mem.req_tag(0).toBool, prefetch_addr, io.icache.req_addr);
val pdq_reset = Reg(resetVal = Bool(true));
pdq_reset <== demand_miss & ~hit | (state === s_bad_resp_wait);
val fill_cnt = Reg(resetVal = UFix(0, 2));
val fill_cnt = Reg(resetVal = UFix(0,2));
when (ip_mem_resp_val.toBool) { fill_cnt <== fill_cnt + UFix(1,1); }
val fill_done = (fill_cnt === UFix(3,2)) & ip_mem_resp_val;
val forward = Reg(resetVal = Bool(false));
val forward_cnt = Reg(resetVal = UFix(0, 2));
val forward_cnt = Reg(resetVal = UFix(0,2));
when (forward & pdq.io.deq_val) { forward_cnt <== forward_cnt + UFix(1,1); }
val forward_done = (forward_cnt === UFix(3, 2)) & pdq.io.deq_val;
val forward_done = (forward_cnt === UFix(3,2)) & pdq.io.deq_val;
forward <== (demand_miss & hit | forward & ~forward_done);
io.icache.resp_val := (io.mem.resp_val && !io.mem.resp_tag.toBool) || (forward && pdq.io.deq_val);
io.icache.resp_val := (io.mem.resp_val && !io.mem.resp_tag(0).toBool) || (forward && pdq.io.deq_val);
io.icache.resp_data := Mux(forward, pdq.io.deq_bits, io.mem.resp_data);
pdq.io.q_reset := pdq_reset;