From bc44572d99ea873539c93edbb60183c49d561daa Mon Sep 17 00:00:00 2001 From: Rimas Avizienis Date: Wed, 30 Nov 2011 21:54:55 -0800 Subject: [PATCH] bugfixes due to new hcl jar file --- rocket/src/main/scala/consts.scala | 2 +- rocket/src/main/scala/dpath.scala | 13 +++++-------- rocket/src/main/scala/icache_prefetch.scala | 14 +++++++------- 3 files changed, 13 insertions(+), 16 deletions(-) diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index 4d28d5aa..5a0ee148 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -199,4 +199,4 @@ object Constants val HAVE_VEC = Bool(false); } -} \ No newline at end of file +} diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index 97a9af33..56c044d8 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -45,7 +45,7 @@ class rocketDpath extends Component val alu = new rocketDpathALU(); val ex_alu_out = alu.io.out; - val ex_jr_target = ex_alu_out(VADDR_BITS,0); + val ex_jr_target = ex_alu_out(VADDR_BITS-1,0); val div = new rocketDivider(64); val div_result = div.io.div_result_bits; @@ -57,10 +57,10 @@ class rocketDpath extends Component val mul_result_tag = mul.io.result_tag; val mul_result_val = mul.io.result_val; - val rfile = new rocketDpathRegfile(); + val rfile = new rocketDpathRegfile(); // instruction fetch definitions - val if_reg_pc = Reg(resetVal = UFix(0,VADDR_BITS)); + val if_reg_pc = Reg(resetVal = UFix(START_ADDR,VADDR_BITS)); // instruction decode definitions val id_reg_valid = Reg(resetVal = Bool(false)); @@ -141,15 +141,12 @@ class rocketDpath extends Component Mux(io.ctrl.sel_pc === PC_BR, ex_branch_target, Mux(io.ctrl.sel_pc === PC_J, ex_branch_target, Mux(io.ctrl.sel_pc === PC_JR, ex_jr_target.toUFix, - Mux(io.ctrl.sel_pc === PC_PCR, mem_reg_wdata, // only used for ERET + Mux(io.ctrl.sel_pc === PC_PCR, mem_reg_wdata(VADDR_BITS-1,0), // only used for ERET Mux(io.ctrl.sel_pc === PC_EVEC, pcr.io.evec, Mux(io.ctrl.sel_pc === PC_MEM, mem_reg_pc, UFix(0, VADDR_BITS))))))))))); - when (!io.host.start){ - if_reg_pc <== UFix(START_ADDR, VADDR_BITS); - } - when (!io.ctrl.stallf) { + when (!io.ctrl.stallf && io.host.start) { if_reg_pc <== if_next_pc.toUFix; } diff --git a/rocket/src/main/scala/icache_prefetch.scala b/rocket/src/main/scala/icache_prefetch.scala index fe7b761c..a0dd4837 100644 --- a/rocket/src/main/scala/icache_prefetch.scala +++ b/rocket/src/main/scala/icache_prefetch.scala @@ -40,23 +40,23 @@ class rocketIPrefetcher extends Component() { val ip_mem_resp_val = io.mem.resp_val && io.mem.resp_tag(0).toBool; io.mem.req_val := io.icache.req_val & ~hit | (state === s_req_wait); - io.mem.req_tag := !(io.icache.req_val && !hit); - io.mem.req_addr := Mux(io.mem.req_tag.toBool, prefetch_addr, io.icache.req_addr); + io.mem.req_tag := Cat(Bits(0,2), !(io.icache.req_val && !hit)); + io.mem.req_addr := Mux(io.mem.req_tag(0).toBool, prefetch_addr, io.icache.req_addr); val pdq_reset = Reg(resetVal = Bool(true)); pdq_reset <== demand_miss & ~hit | (state === s_bad_resp_wait); - val fill_cnt = Reg(resetVal = UFix(0, 2)); + val fill_cnt = Reg(resetVal = UFix(0,2)); when (ip_mem_resp_val.toBool) { fill_cnt <== fill_cnt + UFix(1,1); } val fill_done = (fill_cnt === UFix(3,2)) & ip_mem_resp_val; val forward = Reg(resetVal = Bool(false)); - val forward_cnt = Reg(resetVal = UFix(0, 2)); + val forward_cnt = Reg(resetVal = UFix(0,2)); when (forward & pdq.io.deq_val) { forward_cnt <== forward_cnt + UFix(1,1); } - val forward_done = (forward_cnt === UFix(3, 2)) & pdq.io.deq_val; + val forward_done = (forward_cnt === UFix(3,2)) & pdq.io.deq_val; forward <== (demand_miss & hit | forward & ~forward_done); - io.icache.resp_val := (io.mem.resp_val && !io.mem.resp_tag.toBool) || (forward && pdq.io.deq_val); + io.icache.resp_val := (io.mem.resp_val && !io.mem.resp_tag(0).toBool) || (forward && pdq.io.deq_val); io.icache.resp_data := Mux(forward, pdq.io.deq_bits, io.mem.resp_data); pdq.io.q_reset := pdq_reset; @@ -89,4 +89,4 @@ class rocketIPrefetcher extends Component() { } } -} \ No newline at end of file +}