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coreplex: width adapter should happen as part of coherence manager

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In the future we will want the L2 to be wider on the backside so that
we can take advantage of fat DDR controllers (256bits/beat).
This commit is contained in:
Wesley W. Terpstra
2016-11-22 15:12:45 -08:00
parent a140b07009
commit bbabcf67ff
1 changed files with 4 additions and 4 deletions
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8
src/main/scala/coreplex/BaseCoreplex.scala
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@ -29,10 +29,10 @@ case object BroadcastConfig extends Field[BroadcastConfig]
case class BankedL2Config(
nMemoryChannels: Int = 1,
nBanksPerChannel: Int = 1,
coherenceManager: (Int, Parameters) => (TLInwardNode, TLOutwardNode) = { case (lineBytes, p) =>
coherenceManager: Parameters => (TLInwardNode, TLOutwardNode) = { case p =>
val BroadcastConfig(nTrackers, bufferless) = p(BroadcastConfig)
val bh = LazyModule(new TLBroadcast(lineBytes, nTrackers, bufferless))
(bh.node, bh.node)
val bh = LazyModule(new TLBroadcast(p(CacheBlockBytes), nTrackers, bufferless))
(bh.node, TLWidthWidget(p(L1toL2Config).beatBytes)(bh.node))
}) {
val nBanks = nMemoryChannels*nBanksPerChannel
}
@ -130,7 +130,7 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork {
output := bankBar.node
val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes)
for (i <- 0 until l2Config.nBanksPerChannel) {
val (in, out) = l2Config.coherenceManager(l1tol2_lineBytes, p)
val (in, out) = l2Config.coherenceManager(p)
in := TLFilter(AddressSet(i * l1tol2_lineBytes, mask))(l1tol2.node)
bankBar.node := out
}