From bbabcf67fffa84100332d839e8d365abf2884bb5 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 22 Nov 2016 15:12:45 -0800 Subject: [PATCH] coreplex: width adapter should happen as part of coherence manager In the future we will want the L2 to be wider on the backside so that we can take advantage of fat DDR controllers (256bits/beat). --- src/main/scala/coreplex/BaseCoreplex.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala index 75325802..6b43acec 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/coreplex/BaseCoreplex.scala @@ -29,10 +29,10 @@ case object BroadcastConfig extends Field[BroadcastConfig] case class BankedL2Config( nMemoryChannels: Int = 1, nBanksPerChannel: Int = 1, - coherenceManager: (Int, Parameters) => (TLInwardNode, TLOutwardNode) = { case (lineBytes, p) => + coherenceManager: Parameters => (TLInwardNode, TLOutwardNode) = { case p => val BroadcastConfig(nTrackers, bufferless) = p(BroadcastConfig) - val bh = LazyModule(new TLBroadcast(lineBytes, nTrackers, bufferless)) - (bh.node, bh.node) + val bh = LazyModule(new TLBroadcast(p(CacheBlockBytes), nTrackers, bufferless)) + (bh.node, TLWidthWidget(p(L1toL2Config).beatBytes)(bh.node)) }) { val nBanks = nMemoryChannels*nBanksPerChannel } @@ -130,7 +130,7 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork { output := bankBar.node val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes) for (i <- 0 until l2Config.nBanksPerChannel) { - val (in, out) = l2Config.coherenceManager(l1tol2_lineBytes, p) + val (in, out) = l2Config.coherenceManager(p) in := TLFilter(AddressSet(i * l1tol2_lineBytes, mask))(l1tol2.node) bankBar.node := out }