rocketchip: use TileLink2 interrupts
This commit is contained in:
Wesley W. Terpstra
@ -6,9 +6,11 @@ import Chisel._
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import Chisel.ImplicitConversions._
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import junctions._
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import diplomacy._
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import regmapper._
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import uncore.tilelink2._
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import cde.Parameters
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import scala.math.min
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class GatewayPLICIO extends Bundle {
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val valid = Bool(OUTPUT)
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@ -49,113 +51,161 @@ object PLICConsts
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require(hartBase >= enableBase(maxHarts))
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}
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case class PLICConfig(nHartsIn: Int, supervisor: Boolean, nDevices: Int, nPriorities: Int) {
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import PLICConsts._
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def contextsPerHart = if (supervisor) 2 else 1
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def nHarts = contextsPerHart * nHartsIn
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def context(i: Int, mode: Char) = mode match {
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case 'M' => i * contextsPerHart
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case 'S' => require(supervisor); i * contextsPerHart + 1
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}
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def claimAddr(i: Int, mode: Char) = hartBase(context(i, mode)) + claimOffset
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def threshAddr(i: Int, mode: Char) = hartBase(context(i, mode))
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def enableAddr(i: Int, mode: Char) = enableBase(context(i, mode))
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require(nDevices <= maxDevices)
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require(nHarts > 0 && nHarts <= maxHarts)
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require(nPriorities >= 0 && nPriorities <= nDevices)
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}
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trait HasPLICParameters {
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val params: (() => PLICConfig, Parameters)
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val cfg = params._1 ()
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implicit val p = params._2
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}
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trait PLICBundle extends Bundle with HasPLICParameters {
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val devices = Vec(cfg.nDevices, new GatewayPLICIO).flip
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val harts = Vec(cfg.nHarts, Bool()).asOutput
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}
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trait PLICModule extends Module with HasRegMap with HasPLICParameters {
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val io: PLICBundle
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val priority =
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if (cfg.nPriorities > 0) Reg(Vec(cfg.nDevices+1, UInt(width=log2Up(cfg.nPriorities+1))))
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else Wire(init=Vec.fill(cfg.nDevices+1)(UInt(1)))
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val threshold =
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if (cfg.nPriorities > 0) Reg(Vec(cfg.nHarts, UInt(width = log2Up(cfg.nPriorities+1))))
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else Wire(init=Vec.fill(cfg.nHarts)(UInt(0)))
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val pending = Reg(init=Vec.fill(cfg.nDevices+1){Bool(false)})
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val enables = Reg(Vec(cfg.nHarts, Vec(cfg.nDevices+1, Bool())))
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for ((p, g) <- pending.tail zip io.devices) {
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g.ready := !p
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g.complete := false
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when (g.valid) { p := true }
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}
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def findMax(x: Seq[UInt]): (UInt, UInt) = {
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if (x.length > 1) {
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val half = 1 << (log2Ceil(x.length) - 1)
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val lMax = findMax(x take half)
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val rMax = findMax(x drop half)
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val useLeft = lMax._1 >= rMax._1
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(Mux(useLeft, lMax._1, rMax._1), Mux(useLeft, lMax._2, UInt(half) | rMax._2))
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} else (x.head, UInt(0))
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}
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val maxDevs = Reg(Vec(cfg.nHarts, UInt(width = log2Up(pending.size))))
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for (hart <- 0 until cfg.nHarts) {
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val effectivePriority =
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for (((p, en), pri) <- (pending zip enables(hart) zip priority).tail)
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yield Cat(p && en, pri)
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val (maxPri, maxDev) = findMax((UInt(1) << priority(0).getWidth) +: effectivePriority)
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maxDevs(hart) := maxDev
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io.harts(hart) := Reg(next = maxPri) > Cat(UInt(1), threshold(hart))
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}
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def priorityRegField(x: UInt) = if (cfg.nPriorities > 0) RegField(32, x) else RegField.r(32, x)
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val priorityRegFields = Seq(PLICConsts.priorityBase -> priority.map(p => priorityRegField(p)))
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val pendingRegFields = Seq(PLICConsts.pendingBase -> pending .map(b => RegField.r(1, b)))
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val enableRegFields = enables.zipWithIndex.map { case (e, i) =>
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PLICConsts.enableBase(i) -> e.map(b => RegField(1, b))
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}
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val hartRegFields = Seq.tabulate(cfg.nHarts) { i =>
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PLICConsts.hartBase(i) -> Seq(
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priorityRegField(threshold(i)),
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RegField(32,
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RegReadFn { valid =>
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when (valid) {
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pending(maxDevs(i)) := Bool(false)
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maxDevs(i) := UInt(0) // flush pipeline
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}
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(Bool(true), maxDevs(i))
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},
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RegWriteFn { (valid, data) =>
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when (valid && enables(i)(data)) {
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io.devices(data - UInt(1)).complete := Bool(true)
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}
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Bool(true)
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}
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)
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)
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}
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regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*)
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priority(0) := 0
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pending(0) := false
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for (e <- enables)
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e(0) := false
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}
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/** Platform-Level Interrupt Controller */
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class TLPLIC(c: () => PLICConfig, address: BigInt = 0xC000000)(implicit val p: Parameters)
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extends TLRegisterRouter(address, size = PLICConsts.size, beatBytes = p(rocket.XLen)/8, undefZero = false)(
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new TLRegBundle((c, p), _) with PLICBundle)(
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new TLRegModule((c, p), _, _) with PLICModule)
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class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC000000)(implicit val p: Parameters) extends LazyModule
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{
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val contextsPerHart = if (supervisor) 2 else 1
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require (maxPriorities >= 0)
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val node = TLRegisterNode(
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address = AddressSet(address, PLICConsts.size-1),
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beatBytes = p(rocket.XLen)/8,
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undefZero = false)
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val intnode = IntAdapterNode(
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numSourcePorts = 0 to 1024,
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numSinkPorts = 0 to 1024,
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sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(contextsPerHart))) },
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sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) })
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val tl_in = node.bundleIn
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val devices = intnode.bundleIn
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val harts = intnode.bundleOut
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}
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// Assign all the devices unique ranges
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val sources = intnode.edgesIn.map(_.source)
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val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map {
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case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
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}.flatten
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// Compact the interrupt vector the same way
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val interrupts = (intnode.edgesIn zip io.devices).map { case (e, i) => i.take(e.source.num) }.flatten
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// This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence
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val harts = io.harts.flatten
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println("\nInterrupt map:")
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flatSources.foreach { s =>
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println(s" [${s.range.start}, ${s.range.end}) => ${s.name}")
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}
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val nDevices = interrupts.size
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val nPriorities = min(maxPriorities, nDevices)
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val nHarts = harts.size
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require(nDevices <= PLICConsts.maxDevices)
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require(nHarts > 0 && nHarts <= PLICConsts.maxHarts)
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def context(i: Int, mode: Char) = mode match {
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case 'M' => i * contextsPerHart
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case 'S' => require(supervisor); i * contextsPerHart + 1
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}
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def claimAddr(i: Int, mode: Char) = address + PLICConsts.hartBase(context(i, mode)) + PLICConsts.claimOffset
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def threshAddr(i: Int, mode: Char) = address + PLICConsts.hartBase(context(i, mode))
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def enableAddr(i: Int, mode: Char) = address + PLICConsts.enableBase(context(i, mode))
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// Create the global PLIC config string
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val globalConfigString = Seq(
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s"plic {\n",
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s" priority 0x${address.toString(16)};\n",
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s" pending 0x${(address + PLICConsts.pendingBase).toString(16)};\n",
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s" ndevs ${nDevices};\n",
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s"};\n").mkString
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// Create the per-Hart config string
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val hartConfigStrings = io.harts.zipWithIndex.map { case (_, i) => (Seq(
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s" plic {\n",
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s" m {\n",
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s" ie 0x${enableAddr(i, 'M').toString(16)};\n",
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s" thresh 0x${threshAddr(i, 'M').toString(16)};\n",
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s" claim 0x${claimAddr(i, 'M').toString(16)};\n",
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s" };\n") ++ (if (!supervisor) Seq() else Seq(
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s" s {\n",
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s" ie 0x${enableAddr(i, 'S').toString(16)};\n",
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s" thresh 0x${threshAddr(i, 'S').toString(16)};\n",
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s" claim 0x${claimAddr(i, 'S').toString(16)};\n",
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s" };\n")) ++ Seq(
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s" };\n")).mkString
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}
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// For now, use LevelGateways for all TL2 interrupts
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val gateways = Vec(interrupts.map { case i =>
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val gateway = Module(new LevelGateway)
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gateway.io.interrupt := i
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gateway.io.plic
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})
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val priority =
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if (nPriorities > 0) Reg(Vec(nDevices+1, UInt(width=log2Up(nPriorities+1))))
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else Wire(init=Vec.fill(nDevices+1)(UInt(1)))
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val threshold =
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if (nPriorities > 0) Reg(Vec(nHarts, UInt(width = log2Up(nPriorities+1))))
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else Wire(init=Vec.fill(nHarts)(UInt(0)))
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val pending = Reg(init=Vec.fill(nDevices+1){Bool(false)})
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val enables = Reg(Vec(nHarts, Vec(nDevices+1, Bool())))
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for ((p, g) <- pending.tail zip gateways) {
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g.ready := !p
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g.complete := false
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when (g.valid) { p := true }
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}
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def findMax(x: Seq[UInt]): (UInt, UInt) = {
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if (x.length > 1) {
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val half = 1 << (log2Ceil(x.length) - 1)
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val lMax = findMax(x take half)
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val rMax = findMax(x drop half)
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val useLeft = lMax._1 >= rMax._1
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(Mux(useLeft, lMax._1, rMax._1), Mux(useLeft, lMax._2, UInt(half) | rMax._2))
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} else (x.head, UInt(0))
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}
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val maxDevs = Reg(Vec(nHarts, UInt(width = log2Up(pending.size))))
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for (hart <- 0 until nHarts) {
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val effectivePriority =
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for (((p, en), pri) <- (pending zip enables(hart) zip priority).tail)
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yield Cat(p && en, pri)
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val (maxPri, maxDev) = findMax((UInt(1) << priority(0).getWidth) +: effectivePriority)
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maxDevs(hart) := maxDev
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harts(hart) := Reg(next = maxPri) > Cat(UInt(1), threshold(hart))
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}
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def priorityRegField(x: UInt) = if (nPriorities > 0) RegField(32, x) else RegField.r(32, x)
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val priorityRegFields = Seq(PLICConsts.priorityBase -> priority.map(p => priorityRegField(p)))
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val pendingRegFields = Seq(PLICConsts.pendingBase -> pending .map(b => RegField.r(1, b)))
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val enableRegFields = enables.zipWithIndex.map { case (e, i) =>
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PLICConsts.enableBase(i) -> e.map(b => RegField(1, b))
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}
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val hartRegFields = Seq.tabulate(nHarts) { i =>
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PLICConsts.hartBase(i) -> Seq(
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priorityRegField(threshold(i)),
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RegField(32,
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RegReadFn { valid =>
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when (valid) {
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pending(maxDevs(i)) := Bool(false)
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maxDevs(i) := UInt(0) // flush pipeline
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}
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(Bool(true), maxDevs(i))
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},
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RegWriteFn { (valid, data) =>
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when (valid && enables(i)(data)) {
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gateways(data - UInt(1)).complete := Bool(true)
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}
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Bool(true)
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}
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)
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)
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}
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node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*)
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priority(0) := 0
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pending(0) := false
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for (e <- enables)
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e(0) := false
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}
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}
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@ -6,6 +6,7 @@ import Chisel._
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import junctions._
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import junctions.NastiConstants._
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import regmapper._
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import diplomacy._
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import uncore.tilelink2._
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import uncore.util._
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import util._
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@ -20,22 +21,19 @@ class CoreplexLocalInterrupts extends Bundle {
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val msip = Bool()
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}
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case class CoreplexLocalInterrupterConfig(address: BigInt = 0x02000000) {
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object ClintConsts
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{
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def msipOffset(hart: Int) = hart * msipBytes
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def msipAddress(hart: Int) = address + msipOffset(hart)
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def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes
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def timecmpAddress(hart: Int) = address + timecmpOffset(hart)
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def timeOffset = 0xbff8
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def timeAddress = address + timeOffset
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def msipBytes = 4
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def timecmpBytes = 8
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def size = 0x10000
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}
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trait MixCoreplexLocalInterrupterParameters {
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val params: (CoreplexLocalInterrupterConfig, Parameters)
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val c = params._1
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implicit val p = params._2
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val params: Parameters
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implicit val p = params
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}
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trait CoreplexLocalInterrupterBundle extends Bundle with MixCoreplexLocalInterrupterParameters {
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@ -45,6 +43,7 @@ trait CoreplexLocalInterrupterBundle extends Bundle with MixCoreplexLocalInterru
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trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCoreplexLocalInterrupterParameters {
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val io: CoreplexLocalInterrupterBundle
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val address: AddressSet
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val timeWidth = 64
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val regWidth = 32
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@ -64,6 +63,15 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep
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tile.mtip := time.asUInt >= timecmp(i).asUInt
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}
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val globalConfigString = Seq(
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s"rtc {\n",
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s" addr 0x${(address.base + ClintConsts.timeOffset).toString(16)};\n",
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s"};\n").mkString
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val hartConfigStrings = (0 until p(NTiles)).map { i => Seq(
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s" timecmp 0x${(address.base + ClintConsts.timecmpOffset(i)).toString(16)};\n",
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s" ipi 0x${(address.base + ClintConsts.msipOffset(i)).toString(16)};\n").mkString
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}
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/* 0000 msip hart 0
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* 0004 msip hart 1
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* 4000 mtimecmp hart 0 lo
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@ -75,16 +83,16 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep
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*/
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regmap(
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0 -> makeRegFields(ipi),
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c.timecmpOffset(0) -> makeRegFields(timecmp.flatten),
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c.timeOffset -> makeRegFields(time))
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0 -> makeRegFields(ipi),
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ClintConsts.timecmpOffset(0) -> makeRegFields(timecmp.flatten),
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ClintConsts.timeOffset -> makeRegFields(time))
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def makeRegFields(s: Seq[UInt]) = s.map(r => RegField(regWidth, r))
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}
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/** Power, Reset, Clock, Interrupt */
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// Magic TL2 Incantation to create a TL2 Slave
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class CoreplexLocalInterrupter(c: CoreplexLocalInterrupterConfig)(implicit val p: Parameters)
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extends TLRegisterRouter(c.address, size = c.size, beatBytes = p(rocket.XLen)/8, undefZero = false)(
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new TLRegBundle((c, p), _) with CoreplexLocalInterrupterBundle)(
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new TLRegModule((c, p), _, _) with CoreplexLocalInterrupterModule)
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class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit val p: Parameters)
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extends TLRegisterRouter(address, size = ClintConsts.size, beatBytes = p(rocket.XLen)/8, undefZero = false)(
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new TLRegBundle(p, _) with CoreplexLocalInterrupterBundle)(
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new TLRegModule(p, _, _) with CoreplexLocalInterrupterModule)
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Reference in New Issue
Block a user