rocketchip: use TileLink2 interrupts
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@ -88,21 +88,12 @@ object GenerateGlobalAddrMap {
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}
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object GenerateConfigString {
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def apply(p: Parameters, peripheryManagers: Seq[TLManagerParameters]) = {
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def apply(p: Parameters, clint: CoreplexLocalInterrupter, plic: TLPLIC, peripheryManagers: Seq[TLManagerParameters]) = {
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val c = CoreplexParameters()(p)
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val addrMap = p(GlobalAddrMap)
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val plicAddr = addrMap("TL2:plic").start
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val clint = CoreplexLocalInterrupterConfig()
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val xLen = p(XLen)
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val res = new StringBuilder
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res append "plic {\n"
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res append s" priority 0x${plicAddr.toString(16)};\n"
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res append s" pending 0x${(plicAddr + PLICConsts.pendingBase).toString(16)};\n"
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res append s" ndevs ${c.plicKey.nDevices};\n"
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res append "};\n"
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res append "rtc {\n"
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res append s" addr 0x${clint.timeAddress.toString(16)};\n"
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res append "};\n"
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res append plic.module.globalConfigString
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res append clint.module.globalConfigString
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if (addrMap contains "mem") {
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res append "ram {\n"
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res append " 0 {\n"
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@ -124,22 +115,8 @@ object GenerateConfigString {
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res append s" $i {\n"
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res append " 0 {\n"
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res append s" isa $isa;\n"
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res append s" timecmp 0x${clint.timecmpAddress(i).toString(16)};\n"
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res append s" ipi 0x${clint.msipAddress(i).toString(16)};\n"
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res append s" plic {\n"
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res append s" m {\n"
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res append s" ie 0x${(plicAddr + c.plicKey.enableAddr(i, 'M')).toString(16)};\n"
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res append s" thresh 0x${(plicAddr + c.plicKey.threshAddr(i, 'M')).toString(16)};\n"
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res append s" claim 0x${(plicAddr + c.plicKey.claimAddr(i, 'M')).toString(16)};\n"
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res append s" };\n"
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if (c.hasSupervisor) {
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res append s" s {\n"
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res append s" ie 0x${(plicAddr + c.plicKey.enableAddr(i, 'S')).toString(16)};\n"
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res append s" thresh 0x${(plicAddr + c.plicKey.threshAddr(i, 'S')).toString(16)};\n"
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res append s" claim 0x${(plicAddr + c.plicKey.claimAddr(i, 'S')).toString(16)};\n"
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res append s" };\n"
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}
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res append " };\n"
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res append clint.module.hartConfigStrings(i)
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res append plic.module.hartConfigStrings(i)
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res append " };\n"
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res append " };\n"
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}
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