riscv/rocket-chip
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rocketchip: use TileLink2 interrupts

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Wesley W. Terpstra committed 2016-10-31 11:42:47 -07:00
1 parent 6505431eac
commit ba529c3716
10 files changed
+270 -214
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src/main/scala/rocketchip/TestHarness.scala
+1 -1
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@@ -26,7 +26,7 @@ class TestHarness(q: Parameters) extends Module {
require(dut.io.bus_clk.isEmpty)
require(dut.io.bus_rst.isEmpty)
for (int <- dut.io.interrupts)
for (int <- dut.io.interrupts(0))
int := Bool(false)
if (dut.io.mem_axi.nonEmpty) {