riscv/rocket-chip
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rocketchip: use TileLink2 interrupts

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This commit is contained in:
Wesley W. Terpstra
2016-10-28 21:20:49 -07:00
parent 6505431eac
commit ba529c3716
10 changed files with 270 additions and 214 deletions
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2
src/main/scala/rocketchip/TestHarness.scala
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@ -26,7 +26,7 @@ class TestHarness(q: Parameters) extends Module {
require(dut.io.bus_clk.isEmpty)
require(dut.io.bus_rst.isEmpty)
for (int <- dut.io.interrupts)
for (int <- dut.io.interrupts(0))
int := Bool(false)
if (dut.io.mem_axi.nonEmpty) {