riscv/rocket-chip
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rocketchip: use TileLink2 interrupts

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This commit is contained in:
Wesley W. Terpstra
2016-10-28 21:20:49 -07:00
parent 6505431eac
commit ba529c3716
10 changed files with 270 additions and 214 deletions
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14
src/main/scala/rocketchip/BaseTop.scala
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@ -16,14 +16,12 @@ import coreplex._
// the following parameters will be refactored properly with TL2
case object GlobalAddrMap extends Field[AddrMap]
case object NCoreplexExtClients extends Field[Int]
case object NExtInterrupts extends Field[Int]
/** Enable or disable monitoring of Diplomatic buses */
case object TLEmitMonitors extends Field[Bool]
/** Base Top with no Periphery */
abstract class BaseTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit q: Parameters) extends LazyModule {
// the following variables will be refactored properly with TL2
val pInterrupts = new RangeManager
val pBusMasters = new RangeManager
TLImp.emitMonitors = q(TLEmitMonitors)
@ -31,11 +29,11 @@ abstract class BaseTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(impli
// Add a SoC and peripheral bus
val socBus = LazyModule(new TLXbar)
val peripheryBus = LazyModule(new TLXbar)
val intBus = LazyModule(new IntXbar)
// Fill in the TL1 legacy parameters
implicit val p = q.alterPartial {
case NCoreplexExtClients => pBusMasters.sum
case NExtInterrupts => pInterrupts.sum
case GlobalAddrMap => legacyAddrMap
}
@ -64,7 +62,6 @@ abstract class BaseTopModule[+B <: BaseTopBundle[BaseTop[BaseCoreplex]]](val io:
val coreplexMem : Vec[ClientUncachedTileLinkIO] = Wire(outer.coreplex.module.io.mem)
val coreplexSlave : Vec[ClientUncachedTileLinkIO] = Wire(outer.coreplex.module.io.slave)
val coreplexDebug : DebugBusIO = Wire(outer.coreplex.module.io.debug)
val coreplexInterrupts : Vec[Bool] = Wire(outer.coreplex.module.io.interrupts)
println("Generated Address Map")
for (entry <- p(GlobalAddrMap).flatten) {
@ -79,17 +76,16 @@ abstract class BaseTopModule[+B <: BaseTopBundle[BaseTop[BaseCoreplex]]](val io:
println(f"\t$name%s $start%x - $end%x, $protStr$cacheable")
}
println("\nGenerated Interrupt Vector")
outer.pInterrupts.print
io.success := outer.coreplex.module.io.success
}
trait DirectConnection {
val coreplex: BaseCoreplex
val socBus: TLXbar
val intBus: IntXbar
socBus.node := coreplex.mmio
coreplex.mmioInt := intBus.intnode
}
trait DirectConnectionModule {
@ -98,10 +94,8 @@ trait DirectConnectionModule {
val coreplexMem : Vec[ClientUncachedTileLinkIO]
val coreplexSlave : Vec[ClientUncachedTileLinkIO]
val coreplexDebug : DebugBusIO
val coreplexInterrupts : Vec[Bool]
coreplexMem <> outer.coreplex.module.io.mem
coreplexInterrupts <> outer.coreplex.module.io.interrupts
coreplexMem <> outer.coreplex.module.io.mem
outer.coreplex.module.io.slave <> coreplexSlave
outer.coreplex.module.io.debug <> coreplexDebug
}

25
src/main/scala/rocketchip/Periphery.scala
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@ -129,28 +129,21 @@ trait PeripheryDebugModule {
trait PeripheryExtInterrupts extends LazyModule {
implicit val p: Parameters
val pInterrupts: RangeManager
val intBus: IntXbar
pInterrupts.add("ext", p(NExtTopInterrupts))
val extInterrupts = IntBlindInputNode(p(NExtTopInterrupts))
val extInterruptXing = LazyModule(new IntXing)
intBus.intnode := extInterruptXing.intnode
extInterruptXing.intnode := extInterrupts
}
trait PeripheryExtInterruptsBundle {
implicit val p: Parameters
val interrupts = Vec(p(NExtTopInterrupts), Bool()).asInput
val outer: PeripheryExtInterrupts
val interrupts = outer.extInterrupts.bundleIn
}
trait PeripheryExtInterruptsModule {
implicit val p: Parameters
val outer: PeripheryExtInterrupts
val io: PeripheryExtInterruptsBundle
val coreplexInterrupts: Vec[Bool]
{
val r = outer.pInterrupts.range("ext")
((r._1 until r._2) zipWithIndex) foreach { case (c, i) =>
coreplexInterrupts(c) := io.interrupts(i)
}
}
}
/////
@ -220,9 +213,7 @@ trait PeripheryMasterAXI4MMIO extends HasPeripheryParameters {
}
trait PeripheryMasterAXI4MMIOBundle extends HasPeripheryParameters {
implicit val p: Parameters
val outer: PeripheryMasterAXI4MMIO
val mmio_axi = outer.mmio_axi4.bundleOut
}

2
src/main/scala/rocketchip/TestHarness.scala
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@ -26,7 +26,7 @@ class TestHarness(q: Parameters) extends Module {
require(dut.io.bus_clk.isEmpty)
require(dut.io.bus_rst.isEmpty)
for (int <- dut.io.interrupts)
for (int <- dut.io.interrupts(0))
int := Bool(false)
if (dut.io.mem_axi.nonEmpty) {

33
src/main/scala/rocketchip/Utils.scala
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@ -88,21 +88,12 @@ object GenerateGlobalAddrMap {
}
object GenerateConfigString {
def apply(p: Parameters, peripheryManagers: Seq[TLManagerParameters]) = {
def apply(p: Parameters, clint: CoreplexLocalInterrupter, plic: TLPLIC, peripheryManagers: Seq[TLManagerParameters]) = {
val c = CoreplexParameters()(p)
val addrMap = p(GlobalAddrMap)
val plicAddr = addrMap("TL2:plic").start
val clint = CoreplexLocalInterrupterConfig()
val xLen = p(XLen)
val res = new StringBuilder
res append "plic {\n"
res append s" priority 0x${plicAddr.toString(16)};\n"
res append s" pending 0x${(plicAddr + PLICConsts.pendingBase).toString(16)};\n"
res append s" ndevs ${c.plicKey.nDevices};\n"
res append "};\n"
res append "rtc {\n"
res append s" addr 0x${clint.timeAddress.toString(16)};\n"
res append "};\n"
res append plic.module.globalConfigString
res append clint.module.globalConfigString
if (addrMap contains "mem") {
res append "ram {\n"
res append " 0 {\n"
@ -124,22 +115,8 @@ object GenerateConfigString {
res append s" $i {\n"
res append " 0 {\n"
res append s" isa $isa;\n"
res append s" timecmp 0x${clint.timecmpAddress(i).toString(16)};\n"
res append s" ipi 0x${clint.msipAddress(i).toString(16)};\n"
res append s" plic {\n"
res append s" m {\n"
res append s" ie 0x${(plicAddr + c.plicKey.enableAddr(i, 'M')).toString(16)};\n"
res append s" thresh 0x${(plicAddr + c.plicKey.threshAddr(i, 'M')).toString(16)};\n"
res append s" claim 0x${(plicAddr + c.plicKey.claimAddr(i, 'M')).toString(16)};\n"
res append s" };\n"
if (c.hasSupervisor) {
res append s" s {\n"
res append s" ie 0x${(plicAddr + c.plicKey.enableAddr(i, 'S')).toString(16)};\n"
res append s" thresh 0x${(plicAddr + c.plicKey.threshAddr(i, 'S')).toString(16)};\n"
res append s" claim 0x${(plicAddr + c.plicKey.claimAddr(i, 'S')).toString(16)};\n"
res append s" };\n"
}
res append " };\n"
res append clint.module.hartConfigStrings(i)
res append plic.module.hartConfigStrings(i)
res append " };\n"
res append " };\n"
}