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add new Queue singleton

This commit is contained in:
Andrew Waterman 2012-02-29 14:21:42 -08:00
parent 012da6002e
commit b9ec69f8f5
2 changed files with 41 additions and 18 deletions

View File

@ -53,3 +53,37 @@ class queue[T <: Data](entries: Int, pipe: Boolean = false, flushable: Boolean =
io.enq.ready := !maybe_full || enq_ptr != deq_ptr || (if (pipe) io.deq.ready else Bool(false)) io.enq.ready := !maybe_full || enq_ptr != deq_ptr || (if (pipe) io.deq.ready else Bool(false))
io.deq.bits <> Mem(entries, do_enq, enq_ptr, io.enq.bits).read(deq_ptr) io.deq.bits <> Mem(entries, do_enq, enq_ptr, io.enq.bits).read(deq_ptr)
} }
object Queue
{
def apply[T <: Data](enq: ioDecoupled[T], entries: Int = 2, pipe: Boolean = false) = {
val q = (new queue(entries, pipe)) { enq.bits.clone }
q.io.enq <> enq
q.io.deq
}
}
class pipereg[T <: Data]()(data: => T) extends Component
{
val io = new Bundle {
val enq = new ioValid()(data)
val deq = new ioValid()(data).flip
}
//val bits = Reg() { io.enq.bits.clone }
//when (io.enq.valid) {
// bits := io.enq.bits
//}
io.deq.valid := Reg(io.enq.valid, resetVal = Bool(false))
io.deq.bits <> Mem(1, io.enq.valid, UFix(0), io.enq.bits).read(UFix(0))
}
object PipeReg
{
def apply[T <: Data](enq: ioValid[T]) = {
val q = (new pipereg) { enq.bits.clone }
q.io.enq <> enq
q.io.deq
}
}

View File

@ -27,25 +27,14 @@ class Top() extends Component {
arbiter.io.requestor(2) <> htif.io.mem arbiter.io.requestor(2) <> htif.io.mem
val hub = new CoherenceHubNull val hub = new CoherenceHubNull
// connect tile to hub (figure out how to do this more compactly) // connect tile to hub
val xact_init_q = (new queue(2)) { new TransactionInit } hub.io.tile.xact_init <> Queue(arbiter.io.mem.xact_init)
xact_init_q.io.enq <> arbiter.io.mem.xact_init hub.io.tile.xact_init_data <> Queue(arbiter.io.mem.xact_init_data)
xact_init_q.io.deq <> hub.io.tile.xact_init arbiter.io.mem.xact_rep <> Queue(hub.io.tile.xact_rep, 1, pipe = true)
val xact_init_data_q = (new queue(2)) { new TransactionInitData }
xact_init_data_q.io.enq <> arbiter.io.mem.xact_init_data
xact_init_data_q.io.deq <> hub.io.tile.xact_init_data
val xact_rep_q = (new queue(1, pipe = true)) { new TransactionReply }
xact_rep_q.io.enq <> hub.io.tile.xact_rep
xact_rep_q.io.deq <> arbiter.io.mem.xact_rep
// connect hub to memory // connect hub to memory
val mem_req_q = (new queue(2)) { new MemReqCmd } io.mem.req_cmd <> Queue(hub.io.mem.req_cmd)
mem_req_q.io.enq <> hub.io.mem.req_cmd io.mem.req_data <> Queue(hub.io.mem.req_data)
mem_req_q.io.deq <> io.mem.req_cmd hub.io.mem.resp <> PipeReg(io.mem.resp)
val mem_req_data_q = (new queue(2)) { new MemData }
mem_req_data_q.io.enq <> hub.io.mem.req_data
mem_req_data_q.io.deq <> io.mem.req_data
hub.io.mem.resp.valid := Reg(io.mem.resp.valid, resetVal = Bool(false))
hub.io.mem.resp.bits := Reg(io.mem.resp.bits)
if (HAVE_VEC) if (HAVE_VEC)