From b9ec69f8f51523adab16b0ca9d2f650a5f115105 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@eecs.berkeley.edu>
Date: Wed, 29 Feb 2012 14:21:42 -0800
Subject: [PATCH] add new Queue singleton

---
 rocket/src/main/scala/queues.scala | 34 ++++++++++++++++++++++++++++++
 rocket/src/main/scala/top.scala    | 25 ++++++----------------
 2 files changed, 41 insertions(+), 18 deletions(-)

diff --git a/rocket/src/main/scala/queues.scala b/rocket/src/main/scala/queues.scala
index 14f416ba..12f4aeae 100644
--- a/rocket/src/main/scala/queues.scala
+++ b/rocket/src/main/scala/queues.scala
@@ -53,3 +53,37 @@ class queue[T <: Data](entries: Int, pipe: Boolean = false, flushable: Boolean =
   io.enq.ready := !maybe_full || enq_ptr != deq_ptr || (if (pipe) io.deq.ready else Bool(false))
   io.deq.bits <> Mem(entries, do_enq, enq_ptr, io.enq.bits).read(deq_ptr)
 }
+
+object Queue
+{
+  def apply[T <: Data](enq: ioDecoupled[T], entries: Int = 2, pipe: Boolean = false) = {
+    val q = (new queue(entries, pipe)) { enq.bits.clone }
+    q.io.enq <> enq
+    q.io.deq
+  }
+}
+
+class pipereg[T <: Data]()(data: => T) extends Component
+{
+  val io = new Bundle {
+    val enq = new ioValid()(data)
+    val deq = new ioValid()(data).flip
+  }
+
+  //val bits = Reg() { io.enq.bits.clone }
+  //when (io.enq.valid) {
+  //  bits := io.enq.bits
+  //}
+
+  io.deq.valid := Reg(io.enq.valid, resetVal = Bool(false))
+  io.deq.bits <> Mem(1, io.enq.valid, UFix(0), io.enq.bits).read(UFix(0))
+}
+
+object PipeReg
+{
+  def apply[T <: Data](enq: ioValid[T]) = {
+    val q = (new pipereg) { enq.bits.clone }
+    q.io.enq <> enq
+    q.io.deq
+  }
+}
diff --git a/rocket/src/main/scala/top.scala b/rocket/src/main/scala/top.scala
index 7a472a94..52925b3e 100644
--- a/rocket/src/main/scala/top.scala
+++ b/rocket/src/main/scala/top.scala
@@ -27,25 +27,14 @@ class Top() extends Component {
   arbiter.io.requestor(2) <> htif.io.mem
 
   val hub = new CoherenceHubNull
-  // connect tile to hub (figure out how to do this more compactly)
-  val xact_init_q = (new queue(2)) { new TransactionInit }
-  xact_init_q.io.enq <> arbiter.io.mem.xact_init
-  xact_init_q.io.deq <> hub.io.tile.xact_init
-  val xact_init_data_q = (new queue(2)) { new TransactionInitData }
-  xact_init_data_q.io.enq <> arbiter.io.mem.xact_init_data
-  xact_init_data_q.io.deq <> hub.io.tile.xact_init_data
-  val xact_rep_q = (new queue(1, pipe = true)) { new TransactionReply }
-  xact_rep_q.io.enq <> hub.io.tile.xact_rep
-  xact_rep_q.io.deq <> arbiter.io.mem.xact_rep
+  // connect tile to hub
+  hub.io.tile.xact_init <> Queue(arbiter.io.mem.xact_init)
+  hub.io.tile.xact_init_data <> Queue(arbiter.io.mem.xact_init_data)
+  arbiter.io.mem.xact_rep <> Queue(hub.io.tile.xact_rep, 1, pipe = true)
   // connect hub to memory
-  val mem_req_q = (new queue(2)) { new MemReqCmd }
-  mem_req_q.io.enq <> hub.io.mem.req_cmd
-  mem_req_q.io.deq <> io.mem.req_cmd
-  val mem_req_data_q = (new queue(2)) { new MemData }
-  mem_req_data_q.io.enq <> hub.io.mem.req_data
-  mem_req_data_q.io.deq <> io.mem.req_data
-  hub.io.mem.resp.valid := Reg(io.mem.resp.valid, resetVal = Bool(false))
-  hub.io.mem.resp.bits := Reg(io.mem.resp.bits)
+  io.mem.req_cmd <> Queue(hub.io.mem.req_cmd)
+  io.mem.req_data <> Queue(hub.io.mem.req_data)
+  hub.io.mem.resp <> PipeReg(io.mem.resp)
 
 
   if (HAVE_VEC)