riscv/rocket-chip
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Unconditionally write badaddr, possibly to zero

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59d33f6b83
This commit is contained in:
Andrew Waterman
2017-04-11 19:55:14 -07:00
committed by Andrew Waterman
parent bef88c4c30
commit b9e042d2bf
1 changed files with 3 additions and 2 deletions
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5
src/main/scala/rocket/CSR.scala
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@@ -515,6 +515,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
Causes.misaligned_load, Causes.misaligned_store, Causes.misaligned_fetch, Causes.misaligned_load, Causes.misaligned_store, Causes.misaligned_fetch,
Causes.load_access, Causes.store_access, Causes.fetch_access, Causes.load_access, Causes.store_access, Causes.fetch_access,
Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault) Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault)
val badaddr_value = Mux(write_badaddr, io.badaddr, 0.U)
when (trapToDebug) { when (trapToDebug) {
when (!reg_debug) { when (!reg_debug) {
@@ -527,7 +528,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
}.elsewhen (delegate) { }.elsewhen (delegate) {
reg_sepc := formEPC(epc) reg_sepc := formEPC(epc)
reg_scause := cause reg_scause := cause
when (write_badaddr) { reg_sbadaddr := io.badaddr } reg_sbadaddr := badaddr_value
reg_mstatus.spie := reg_mstatus.sie reg_mstatus.spie := reg_mstatus.sie
reg_mstatus.spp := reg_mstatus.prv reg_mstatus.spp := reg_mstatus.prv
reg_mstatus.sie := false reg_mstatus.sie := false
@@ -535,7 +536,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
}.otherwise { }.otherwise {
reg_mepc := formEPC(epc) reg_mepc := formEPC(epc)
reg_mcause := cause reg_mcause := cause
when (write_badaddr) { reg_mbadaddr := io.badaddr } reg_mbadaddr := badaddr_value
reg_mstatus.mpie := reg_mstatus.mie reg_mstatus.mpie := reg_mstatus.mie
reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv) reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv)
reg_mstatus.mie := false reg_mstatus.mie := false