diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala
index 5aa5139d..a975a1ea 100644
--- a/src/main/scala/rocket/CSR.scala
+++ b/src/main/scala/rocket/CSR.scala
@@ -515,6 +515,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
       Causes.misaligned_load, Causes.misaligned_store, Causes.misaligned_fetch,
       Causes.load_access, Causes.store_access, Causes.fetch_access,
       Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault)
+    val badaddr_value = Mux(write_badaddr, io.badaddr, 0.U)
 
     when (trapToDebug) {
       when (!reg_debug) {
@@ -527,7 +528,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
     }.elsewhen (delegate) {
       reg_sepc := formEPC(epc)
       reg_scause := cause
-      when (write_badaddr) { reg_sbadaddr := io.badaddr }
+      reg_sbadaddr := badaddr_value
       reg_mstatus.spie := reg_mstatus.sie
       reg_mstatus.spp := reg_mstatus.prv
       reg_mstatus.sie := false
@@ -535,7 +536,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
     }.otherwise {
       reg_mepc := formEPC(epc)
       reg_mcause := cause
-      when (write_badaddr) { reg_mbadaddr := io.badaddr }
+      reg_mbadaddr := badaddr_value
       reg_mstatus.mpie := reg_mstatus.mie
       reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv)
       reg_mstatus.mie := false