uncore and rocket changes for new xact types
This commit is contained in:
Henry Cook
parent
d9cb96c0ae
commit
b9a9664de5
@ -3,10 +3,39 @@ package rocket
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import Chisel._
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import Constants._
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class TransactionInit extends Bundle {
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object TransactionInit
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{
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def apply(x_type: Bits, addr: UFix, tile_xact_id: UFix) = {
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val init = new TransactionInit
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init.x_type := x_type
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init.addr := addr
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init.tile_xact_id := tile_xact_id
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init
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}
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def apply(x_type: Bits, addr: UFix, tile_xact_id: UFix, write_mask: Bits) = {
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val init = new TransactionInit
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init.x_type := x_type
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init.addr := addr
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init.tile_xact_id := tile_xact_id
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init.write_mask := write_mask
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init
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}
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def apply(x_type: Bits, addr: UFix, tile_xact_id: UFix, subword_addr: UFix, atomic_opcode: UFix) = {
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val init = new TransactionInit
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init.x_type := x_type
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init.addr := addr
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init.tile_xact_id := tile_xact_id
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init.subword_addr := subword_addr
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init.atomic_opcode := atomic_opcode
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init
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}
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}
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class TransactionInit extends PhysicalAddress {
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val x_type = Bits(width = X_INIT_TYPE_MAX_BITS)
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val address = UFix(width = PADDR_BITS - OFFSET_BITS)
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val write_mask = Bits(width = X_INIT_WRITE_MASK_BITS)
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val subword_addr = Bits(width = X_INIT_SUBWORD_ADDR_BITS)
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val atomic_opcode = Bits(width = X_INIT_ATOMIC_OP_BITS)
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}
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class TransactionInitData extends MemData
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@ -15,10 +44,9 @@ class TransactionAbort extends Bundle {
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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}
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class ProbeRequest extends Bundle {
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class ProbeRequest extends PhysicalAddress {
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val p_type = Bits(width = P_REQ_TYPE_MAX_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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val address = Bits(width = PADDR_BITS - OFFSET_BITS)
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}
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class ProbeReply extends Bundle {
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@ -76,6 +104,7 @@ abstract class CoherencePolicy {
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def messageHasData (init: TransactionInit): Bool
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def messageHasData (reply: TransactionReply): Bool
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def messageUpdatesDataArray (reply: TransactionReply): Bool
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def messageIsUncached(init: TransactionInit): Bool
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def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool
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def getTransactionReplyType(x_type: UFix, count: UFix): Bits
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@ -86,8 +115,11 @@ abstract class CoherencePolicy {
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}
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trait UncachedTransactions {
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def getTransactionInitTypeOnUncachedRead(): UFix
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def getTransactionInitTypeOnUncachedWrite(): UFix
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def getUncachedReadTransactionInit(addr: UFix, id: UFix): TransactionInit
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def getUncachedWriteTransactionInit(addr: UFix, id: UFix): TransactionInit
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def getUncachedReadWordTransactionInit(addr: UFix, id: UFix): TransactionInit
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def getUncachedWriteWordTransactionInit(addr: UFix, id: UFix, write_mask: Bits): TransactionInit
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def getUncachedAtomicTransactionInit(addr: UFix, id: UFix, subword_addr: UFix, atomic_op: UFix): TransactionInit
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}
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abstract class CoherencePolicyWithUncached extends CoherencePolicy with UncachedTransactions
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@ -115,6 +147,8 @@ class ThreeStateIncoherence extends IncoherentPolicy {
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val xactInitReadClean :: xactInitReadDirty :: xactInitWriteback :: Nil = Enum(3){ UFix() }
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val xactReplyData :: xactReplyAck :: Nil = Enum(2){ UFix() }
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val probeRepInvalidateAck :: Nil = Enum(1){ UFix() }
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val uncachedTypeList = List()
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val hasDataTypeList = List(xactInitWriteback)
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def isHit ( cmd: Bits, state: UFix): Bool = (state === tileClean || state === tileDirty)
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def isValid (state: UFix): Bool = state != tileInvalid
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@ -149,9 +183,10 @@ class ThreeStateIncoherence extends IncoherentPolicy {
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def getTransactionInitTypeOnCacheControl(cmd: Bits): Bits = xactInitWriteback //TODO
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def getTransactionInitTypeOnWriteback(): Bits = xactInitWriteback
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def messageHasData (init: TransactionInit): Bool = (init.x_type === xactInitWriteback)
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def messageHasData (init: TransactionInit): Bool = hasDataTypeList.map(t => init.x_type === t).reduceLeft(_||_)
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def messageHasData (reply: TransactionReply) = (reply.x_type === xactReplyData)
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def messageUpdatesDataArray (reply: TransactionReply) = (reply.x_type === xactReplyData)
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def messageIsUncached(init: TransactionInit): Bool = uncachedTypeList.map(t => init.x_type === t).reduceLeft(_||_)
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}
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class MICoherence extends CoherencePolicyWithUncached {
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@ -159,10 +194,12 @@ class MICoherence extends CoherencePolicyWithUncached {
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val tileInvalid :: tileValid :: Nil = Enum(2){ UFix() }
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val globalInvalid :: globalValid :: Nil = Enum(2){ UFix() }
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val xactInitReadExclusive :: xactInitReadUncached :: xactInitWriteUncached :: Nil = Enum(3){ UFix() }
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val xactReplyReadExclusive :: xactReplyReadUncached :: xactReplyWriteUncached :: Nil = Enum(3){ UFix() }
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val xactInitReadExclusive :: xactInitReadUncached :: xactInitWriteUncached :: xactInitReadWordUncached :: xactInitWriteWordUncached :: xactInitAtomicUncached :: Nil = Enum(6){ UFix() }
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val xactReplyReadExclusive :: xactReplyReadUncached :: xactReplyWriteUncached :: xactReplyReadWordUncached :: xactReplyWriteWordUncached :: xactReplyAtomicUncached :: Nil = Enum(6){ UFix() }
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val probeReqInvalidate :: probeReqCopy :: Nil = Enum(2){ UFix() }
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val probeRepInvalidateData :: probeRepCopyData :: probeRepInvalidateAck :: probeRepCopyAck :: Nil = Enum(4){ UFix() }
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val uncachedTypeList = List(xactInitReadUncached, xactInitWriteUncached, xactReplyReadWordUncached, xactInitWriteWordUncached, xactInitAtomicUncached)
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val hasDataTypeList = List(xactInitWriteUncached, xactInitWriteWordUncached, xactInitAtomicUncached)
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def isHit (cmd: Bits, state: UFix): Bool = state != tileInvalid
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def isValid (state: UFix): Bool = state != tileInvalid
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@ -191,7 +228,10 @@ class MICoherence extends CoherencePolicyWithUncached {
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MuxLookup(incoming.x_type, tileInvalid, Array(
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xactReplyReadExclusive -> tileValid,
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xactReplyReadUncached -> tileInvalid,
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xactReplyWriteUncached -> tileInvalid
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xactReplyWriteUncached -> tileInvalid,
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xactReplyReadWordUncached -> tileInvalid,
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xactReplyWriteWordUncached -> tileInvalid,
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xactReplyAtomicUncached -> tileInvalid
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))
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}
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def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = {
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@ -201,8 +241,12 @@ class MICoherence extends CoherencePolicyWithUncached {
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))
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}
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def getTransactionInitTypeOnUncachedRead() = xactInitReadUncached
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def getTransactionInitTypeOnUncachedWrite() = xactInitWriteUncached
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def getUncachedReadTransactionInit(addr: UFix, id: UFix) = TransactionInit(xactInitReadUncached, addr, id)
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def getUncachedWriteTransactionInit(addr: UFix, id: UFix) = TransactionInit(xactInitWriteUncached, addr, id)
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def getUncachedReadWordTransactionInit(addr: UFix, id: UFix) = TransactionInit(xactInitReadWordUncached, addr, id)
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def getUncachedWriteWordTransactionInit(addr: UFix, id: UFix, write_mask: Bits) = TransactionInit(xactInitWriteWordUncached, addr, id, write_mask)
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def getUncachedAtomicTransactionInit(addr: UFix, id: UFix, subword_addr: UFix, atomic_op: UFix) = TransactionInit(xactInitAtomicUncached, addr, id, subword_addr, atomic_op)
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def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = xactInitReadExclusive
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def getTransactionInitTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: TransactionInit): UFix = xactInitReadExclusive
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def getTransactionInitTypeOnCacheControl(cmd: Bits): Bits = xactInitWriteUncached
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@ -227,15 +271,14 @@ class MICoherence extends CoherencePolicyWithUncached {
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(reply.p_type === probeRepInvalidateData ||
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reply.p_type === probeRepCopyData)
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}
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def messageHasData (init: TransactionInit): Bool = {
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(init.x_type === xactInitWriteUncached)
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}
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def messageHasData (init: TransactionInit): Bool = hasDataTypeList.map(t => init.x_type === t).reduceLeft(_||_)
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def messageHasData (reply: TransactionReply): Bool = {
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(reply.x_type != xactReplyWriteUncached)
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(reply.x_type != xactReplyWriteUncached && reply.x_type != xactReplyWriteWordUncached)
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}
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def messageUpdatesDataArray (reply: TransactionReply): Bool = {
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(reply.x_type === xactReplyReadExclusive)
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}
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def messageIsUncached(init: TransactionInit): Bool = uncachedTypeList.map(t => init.x_type === t).reduceLeft(_||_)
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def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2)
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@ -243,7 +286,10 @@ class MICoherence extends CoherencePolicyWithUncached {
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MuxLookup(x_type, xactReplyReadUncached, Array(
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xactInitReadExclusive -> xactReplyReadExclusive,
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xactInitReadUncached -> xactReplyReadUncached,
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xactInitWriteUncached -> xactReplyWriteUncached
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xactInitWriteUncached -> xactReplyWriteUncached,
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xactInitReadWordUncached -> xactReplyReadWordUncached,
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xactInitWriteWordUncached -> xactReplyWriteWordUncached,
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xactInitAtomicUncached -> xactReplyAtomicUncached
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))
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}
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@ -251,7 +297,10 @@ class MICoherence extends CoherencePolicyWithUncached {
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MuxLookup(x_type, probeReqCopy, Array(
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xactInitReadExclusive -> probeReqInvalidate,
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xactInitReadUncached -> probeReqCopy,
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xactInitWriteUncached -> probeReqInvalidate
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xactInitWriteUncached -> probeReqInvalidate,
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xactInitReadWordUncached -> probeReqCopy,
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xactInitWriteWordUncached -> probeReqInvalidate,
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xactInitAtomicUncached -> probeReqInvalidate
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))
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}
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@ -271,17 +320,19 @@ class MEICoherence extends CoherencePolicyWithUncached {
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val tileInvalid :: tileExclusiveClean :: tileExclusiveDirty :: Nil = Enum(3){ UFix() }
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val globalInvalid :: globalExclusiveClean :: Nil = Enum(2){ UFix() }
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val xactInitReadExclusiveClean :: xactInitReadExclusiveDirty :: xactInitReadUncached :: xactInitWriteUncached :: Nil = Enum(4){ UFix() }
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val xactReplyReadExclusive :: xactReplyReadUncached :: xactReplyWriteUncached :: xactReplyReadExclusiveAck :: Nil = Enum(4){ UFix() }
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val xactInitReadExclusiveClean :: xactInitReadExclusiveDirty :: xactInitReadUncached :: xactInitWriteUncached :: xactInitReadWordUncached :: xactInitWriteWordUncached :: xactInitAtomicUncached :: Nil = Enum(7){ UFix() }
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val xactReplyReadExclusive :: xactReplyReadUncached :: xactReplyWriteUncached :: xactReplyReadExclusiveAck :: xactReplyReadWordUncached :: xactReplyWriteWordUncached :: xactReplyAtomicUncached :: Nil = Enum(7){ UFix() }
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val probeReqInvalidate :: probeReqDowngrade :: probeReqCopy :: Nil = Enum(3){ UFix() }
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val probeRepInvalidateData :: probeRepDowngradeData :: probeRepCopyData :: probeRepInvalidateAck :: probeRepDowngradeAck :: probeRepCopyAck :: Nil = Enum(6){ UFix() }
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val uncachedTypeList = List(xactInitReadUncached, xactInitWriteUncached, xactReplyReadWordUncached, xactInitWriteWordUncached, xactInitAtomicUncached)
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val hasDataTypeList = List(xactInitWriteUncached, xactInitWriteWordUncached, xactInitAtomicUncached)
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def isHit (cmd: Bits, state: UFix): Bool = state != tileInvalid
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def isValid (state: UFix): Bool = state != tileInvalid
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def needsTransactionOnSecondaryMiss(cmd: Bits, outstanding: TransactionInit): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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(read && (outstanding.x_type === xactInitReadUncached || outstanding.x_type === xactInitWriteUncached)) ||
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(read && messageIsUncached(outstanding)) ||
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(write && (outstanding.x_type != xactInitReadExclusiveDirty))
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}
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def needsTransactionOnCacheControl(cmd: Bits, state: UFix): Bool = {
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@ -311,7 +362,10 @@ class MEICoherence extends CoherencePolicyWithUncached {
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xactReplyReadExclusive -> Mux(outstanding.x_type === xactInitReadExclusiveDirty, tileExclusiveDirty, tileExclusiveClean),
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xactReplyReadExclusiveAck -> tileExclusiveDirty,
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xactReplyReadUncached -> tileInvalid,
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xactReplyWriteUncached -> tileInvalid
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xactReplyWriteUncached -> tileInvalid,
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xactReplyReadWordUncached -> tileInvalid,
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xactReplyWriteWordUncached -> tileInvalid,
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xactReplyAtomicUncached -> tileInvalid
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))
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}
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def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = {
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@ -322,8 +376,12 @@ class MEICoherence extends CoherencePolicyWithUncached {
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))
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}
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def getTransactionInitTypeOnUncachedRead() = xactInitReadUncached
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def getTransactionInitTypeOnUncachedWrite() = xactInitWriteUncached
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def getUncachedReadTransactionInit(addr: UFix, id: UFix) = TransactionInit(xactInitReadUncached, addr, id)
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def getUncachedWriteTransactionInit(addr: UFix, id: UFix) = TransactionInit(xactInitWriteUncached, addr, id)
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def getUncachedReadWordTransactionInit(addr: UFix, id: UFix) = TransactionInit(xactInitReadWordUncached, addr, id)
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def getUncachedWriteWordTransactionInit(addr: UFix, id: UFix, write_mask: Bits) = TransactionInit(xactInitWriteWordUncached, addr, id, write_mask)
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def getUncachedAtomicTransactionInit(addr: UFix, id: UFix, subword_addr: UFix, atomic_op: UFix) = TransactionInit(xactInitAtomicUncached, addr, id, subword_addr, atomic_op)
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def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, xactInitReadExclusiveDirty, xactInitReadExclusiveClean)
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@ -357,15 +415,14 @@ class MEICoherence extends CoherencePolicyWithUncached {
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reply.p_type === probeRepDowngradeData ||
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reply.p_type === probeRepCopyData)
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}
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def messageHasData (init: TransactionInit): Bool = {
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(init.x_type === xactInitWriteUncached)
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}
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def messageHasData (init: TransactionInit): Bool = hasDataTypeList.map(t => init.x_type === t).reduceLeft(_||_)
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def messageHasData (reply: TransactionReply): Bool = {
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(reply.x_type != xactReplyWriteUncached && reply.x_type != xactReplyReadExclusiveAck)
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(reply.x_type != xactReplyWriteUncached && reply.x_type != xactReplyReadExclusiveAck && reply.x_type != xactReplyWriteWordUncached)
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}
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def messageUpdatesDataArray (reply: TransactionReply): Bool = {
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(reply.x_type === xactReplyReadExclusive)
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}
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def messageIsUncached(init: TransactionInit): Bool = uncachedTypeList.map(t => init.x_type === t).reduceLeft(_||_)
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def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2)
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@ -374,7 +431,10 @@ class MEICoherence extends CoherencePolicyWithUncached {
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xactInitReadExclusiveClean -> xactReplyReadExclusive,
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xactInitReadExclusiveDirty -> xactReplyReadExclusive,
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xactInitReadUncached -> xactReplyReadUncached,
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xactInitWriteUncached -> xactReplyWriteUncached
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xactInitWriteUncached -> xactReplyWriteUncached,
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xactInitReadWordUncached -> xactReplyReadWordUncached,
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xactInitWriteWordUncached -> xactReplyWriteWordUncached,
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xactInitAtomicUncached -> xactReplyAtomicUncached
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))
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}
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@ -383,7 +443,10 @@ class MEICoherence extends CoherencePolicyWithUncached {
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xactInitReadExclusiveClean -> probeReqInvalidate,
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xactInitReadExclusiveDirty -> probeReqInvalidate,
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xactInitReadUncached -> probeReqCopy,
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xactInitWriteUncached -> probeReqInvalidate
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xactInitWriteUncached -> probeReqInvalidate,
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xactInitReadWordUncached -> probeReqCopy,
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xactInitWriteWordUncached -> probeReqInvalidate,
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xactInitAtomicUncached -> probeReqInvalidate
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))
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}
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@ -403,10 +466,12 @@ class MSICoherence extends CoherencePolicyWithUncached {
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val tileInvalid :: tileShared :: tileExclusiveDirty :: Nil = Enum(3){ UFix() }
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val globalInvalid :: globalShared :: globalExclusive :: Nil = Enum(3){ UFix() }
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val xactInitReadShared :: xactInitReadExclusive :: xactInitReadUncached :: xactInitWriteUncached :: Nil = Enum(4){ UFix() }
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val xactReplyReadShared :: xactReplyReadExclusive :: xactReplyReadUncached :: xactReplyWriteUncached :: xactReplyReadExclusiveAck :: Nil = Enum(5){ UFix() }
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val xactInitReadShared :: xactInitReadExclusive :: xactInitReadUncached :: xactInitWriteUncached :: xactInitReadWordUncached :: xactInitWriteWordUncached :: xactInitAtomicUncached :: Nil = Enum(7){ UFix() }
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val xactReplyReadShared :: xactReplyReadExclusive :: xactReplyReadUncached :: xactReplyWriteUncached :: xactReplyReadExclusiveAck :: xactReplyReadWordUncached :: xactReplyWriteWordUncached :: xactReplyAtomicUncached :: Nil = Enum(8){ UFix() }
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val probeReqInvalidate :: probeReqDowngrade :: probeReqCopy :: Nil = Enum(3){ UFix() }
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val probeRepInvalidateData :: probeRepDowngradeData :: probeRepCopyData :: probeRepInvalidateAck :: probeRepDowngradeAck :: probeRepCopyAck :: Nil = Enum(6){ UFix() }
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val uncachedTypeList = List(xactInitReadUncached, xactInitWriteUncached, xactReplyReadWordUncached, xactInitWriteWordUncached, xactInitAtomicUncached)
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val hasDataTypeList = List(xactInitWriteUncached, xactInitWriteWordUncached, xactInitAtomicUncached)
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def isHit (cmd: Bits, state: UFix): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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@ -419,7 +484,7 @@ class MSICoherence extends CoherencePolicyWithUncached {
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def needsTransactionOnSecondaryMiss(cmd: Bits, outstanding: TransactionInit): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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(read && (outstanding.x_type === xactInitReadUncached || outstanding.x_type === xactInitWriteUncached)) ||
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(read && messageIsUncached(outstanding)) ||
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(write && (outstanding.x_type != xactInitReadExclusive))
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}
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def needsTransactionOnCacheControl(cmd: Bits, state: UFix): Bool = {
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@ -450,7 +515,10 @@ class MSICoherence extends CoherencePolicyWithUncached {
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xactReplyReadExclusive -> tileExclusiveDirty,
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xactReplyReadExclusiveAck -> tileExclusiveDirty,
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xactReplyReadUncached -> tileInvalid,
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xactReplyWriteUncached -> tileInvalid
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xactReplyWriteUncached -> tileInvalid,
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xactReplyReadWordUncached -> tileInvalid,
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xactReplyWriteWordUncached -> tileInvalid,
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xactReplyAtomicUncached -> tileInvalid
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))
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}
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def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = {
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@ -461,8 +529,12 @@ class MSICoherence extends CoherencePolicyWithUncached {
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))
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}
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def getTransactionInitTypeOnUncachedRead() = xactInitReadUncached
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def getTransactionInitTypeOnUncachedWrite() = xactInitWriteUncached
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def getUncachedReadTransactionInit(addr: UFix, id: UFix) = TransactionInit(xactInitReadUncached, addr, id)
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def getUncachedWriteTransactionInit(addr: UFix, id: UFix) = TransactionInit(xactInitWriteUncached, addr, id)
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def getUncachedReadWordTransactionInit(addr: UFix, id: UFix) = TransactionInit(xactInitReadWordUncached, addr, id)
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def getUncachedWriteWordTransactionInit(addr: UFix, id: UFix, write_mask: Bits) = TransactionInit(xactInitWriteWordUncached, addr, id, write_mask)
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def getUncachedAtomicTransactionInit(addr: UFix, id: UFix, subword_addr: UFix, atomic_op: UFix) = TransactionInit(xactInitAtomicUncached, addr, id, subword_addr, atomic_op)
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def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
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||||
val (read, write) = cpuCmdToRW(cmd)
|
||||
Mux(write || cmd === M_PFW, xactInitReadExclusive, xactInitReadShared)
|
||||
@ -496,15 +568,14 @@ class MSICoherence extends CoherencePolicyWithUncached {
|
||||
reply.p_type === probeRepDowngradeData ||
|
||||
reply.p_type === probeRepCopyData)
|
||||
}
|
||||
def messageHasData (init: TransactionInit): Bool = {
|
||||
(init.x_type === xactInitWriteUncached)
|
||||
}
|
||||
def messageHasData (init: TransactionInit): Bool = hasDataTypeList.map(t => init.x_type === t).reduceLeft(_||_)
|
||||
def messageHasData (reply: TransactionReply): Bool = {
|
||||
(reply.x_type != xactReplyWriteUncached && reply.x_type != xactReplyReadExclusiveAck)
|
||||
(reply.x_type != xactReplyWriteUncached && reply.x_type != xactReplyReadExclusiveAck && reply.x_type != xactReplyWriteWordUncached)
|
||||
}
|
||||
def messageUpdatesDataArray (reply: TransactionReply): Bool = {
|
||||
(reply.x_type === xactReplyReadShared || reply.x_type === xactReplyReadExclusive)
|
||||
}
|
||||
def messageIsUncached(init: TransactionInit): Bool = uncachedTypeList.map(t => init.x_type === t).reduceLeft(_||_)
|
||||
|
||||
def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2)
|
||||
|
||||
@ -513,7 +584,10 @@ class MSICoherence extends CoherencePolicyWithUncached {
|
||||
xactInitReadShared -> Mux(count > UFix(0), xactReplyReadShared, xactReplyReadExclusive),
|
||||
xactInitReadExclusive -> xactReplyReadExclusive,
|
||||
xactInitReadUncached -> xactReplyReadUncached,
|
||||
xactInitWriteUncached -> xactReplyWriteUncached
|
||||
xactInitWriteUncached -> xactReplyWriteUncached,
|
||||
xactInitReadWordUncached -> xactReplyReadWordUncached,
|
||||
xactInitWriteWordUncached -> xactReplyWriteWordUncached,
|
||||
xactInitAtomicUncached -> xactReplyAtomicUncached
|
||||
))
|
||||
}
|
||||
|
||||
@ -542,10 +616,12 @@ class MESICoherence extends CoherencePolicyWithUncached {
|
||||
val tileInvalid :: tileShared :: tileExclusiveClean :: tileExclusiveDirty :: Nil = Enum(4){ UFix() }
|
||||
val globalInvalid :: globalShared :: globalExclusiveClean :: Nil = Enum(3){ UFix() }
|
||||
|
||||
val xactInitReadShared :: xactInitReadExclusive :: xactInitReadUncached :: xactInitWriteUncached :: Nil = Enum(4){ UFix() }
|
||||
val xactReplyReadShared :: xactReplyReadExclusive :: xactReplyReadUncached :: xactReplyWriteUncached :: xactReplyReadExclusiveAck :: Nil = Enum(5){ UFix() }
|
||||
val xactInitReadShared :: xactInitReadExclusive :: xactInitReadUncached :: xactInitWriteUncached :: xactInitReadWordUncached :: xactInitWriteWordUncached :: xactInitAtomicUncached :: Nil = Enum(7){ UFix() }
|
||||
val xactReplyReadShared :: xactReplyReadExclusive :: xactReplyReadUncached :: xactReplyWriteUncached :: xactReplyReadExclusiveAck :: xactReplyReadWordUncached :: xactReplyWriteWordUncached :: xactReplyAtomicUncached :: Nil = Enum(8){ UFix() }
|
||||
val probeReqInvalidate :: probeReqDowngrade :: probeReqCopy :: Nil = Enum(3){ UFix() }
|
||||
val probeRepInvalidateData :: probeRepDowngradeData :: probeRepCopyData :: probeRepInvalidateAck :: probeRepDowngradeAck :: probeRepCopyAck :: Nil = Enum(6){ UFix() }
|
||||
val uncachedTypeList = List(xactInitReadUncached, xactInitWriteUncached, xactReplyReadWordUncached, xactInitWriteWordUncached, xactInitAtomicUncached)
|
||||
val hasDataTypeList = List(xactInitWriteUncached, xactInitWriteWordUncached, xactInitAtomicUncached)
|
||||
|
||||
def isHit (cmd: Bits, state: UFix): Bool = {
|
||||
val (read, write) = cpuCmdToRW(cmd)
|
||||
@ -558,7 +634,7 @@ class MESICoherence extends CoherencePolicyWithUncached {
|
||||
|
||||
def needsTransactionOnSecondaryMiss(cmd: Bits, outstanding: TransactionInit): Bool = {
|
||||
val (read, write) = cpuCmdToRW(cmd)
|
||||
(read && (outstanding.x_type === xactInitReadUncached || outstanding.x_type === xactInitWriteUncached)) ||
|
||||
(read && messageIsUncached(outstanding)) ||
|
||||
(write && (outstanding.x_type != xactInitReadExclusive))
|
||||
}
|
||||
def needsTransactionOnCacheControl(cmd: Bits, state: UFix): Bool = {
|
||||
@ -589,7 +665,10 @@ class MESICoherence extends CoherencePolicyWithUncached {
|
||||
xactReplyReadExclusive -> Mux(outstanding.x_type === xactInitReadExclusive, tileExclusiveDirty, tileExclusiveClean),
|
||||
xactReplyReadExclusiveAck -> tileExclusiveDirty,
|
||||
xactReplyReadUncached -> tileInvalid,
|
||||
xactReplyWriteUncached -> tileInvalid
|
||||
xactReplyWriteUncached -> tileInvalid,
|
||||
xactReplyReadWordUncached -> tileInvalid,
|
||||
xactReplyWriteWordUncached -> tileInvalid,
|
||||
xactReplyAtomicUncached -> tileInvalid
|
||||
))
|
||||
}
|
||||
def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = {
|
||||
@ -600,8 +679,12 @@ class MESICoherence extends CoherencePolicyWithUncached {
|
||||
))
|
||||
}
|
||||
|
||||
def getTransactionInitTypeOnUncachedRead() = xactInitReadUncached
|
||||
def getTransactionInitTypeOnUncachedWrite() = xactInitWriteUncached
|
||||
def getUncachedReadTransactionInit(addr: UFix, id: UFix) = TransactionInit(xactInitReadUncached, addr, id)
|
||||
def getUncachedWriteTransactionInit(addr: UFix, id: UFix) = TransactionInit(xactInitWriteUncached, addr, id)
|
||||
def getUncachedReadWordTransactionInit(addr: UFix, id: UFix) = TransactionInit(xactInitReadWordUncached, addr, id)
|
||||
def getUncachedWriteWordTransactionInit(addr: UFix, id: UFix, write_mask: Bits) = TransactionInit(xactInitWriteWordUncached, addr, id, write_mask)
|
||||
def getUncachedAtomicTransactionInit(addr: UFix, id: UFix, subword_addr: UFix, atomic_op: UFix) = TransactionInit(xactInitAtomicUncached, addr, id, subword_addr, atomic_op)
|
||||
|
||||
def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
|
||||
val (read, write) = cpuCmdToRW(cmd)
|
||||
Mux(write || cmd === M_PFW, xactInitReadExclusive, xactInitReadShared)
|
||||
@ -635,15 +718,14 @@ class MESICoherence extends CoherencePolicyWithUncached {
|
||||
reply.p_type === probeRepDowngradeData ||
|
||||
reply.p_type === probeRepCopyData)
|
||||
}
|
||||
def messageHasData (init: TransactionInit): Bool = {
|
||||
(init.x_type === xactInitWriteUncached)
|
||||
}
|
||||
def messageHasData (init: TransactionInit): Bool = hasDataTypeList.map(t => init.x_type === t).reduceLeft(_||_)
|
||||
def messageHasData (reply: TransactionReply): Bool = {
|
||||
(reply.x_type != xactReplyWriteUncached && reply.x_type != xactReplyReadExclusiveAck)
|
||||
(reply.x_type != xactReplyWriteUncached && reply.x_type != xactReplyReadExclusiveAck && reply.x_type != xactReplyWriteWordUncached)
|
||||
}
|
||||
def messageUpdatesDataArray (reply: TransactionReply): Bool = {
|
||||
(reply.x_type === xactReplyReadShared || reply.x_type === xactReplyReadExclusive)
|
||||
}
|
||||
def messageIsUncached(init: TransactionInit): Bool = uncachedTypeList.map(t => init.x_type === t).reduceLeft(_||_)
|
||||
|
||||
def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2)
|
||||
|
||||
@ -652,7 +734,10 @@ class MESICoherence extends CoherencePolicyWithUncached {
|
||||
xactInitReadShared -> Mux(count > UFix(0), xactReplyReadShared, xactReplyReadExclusive),
|
||||
xactInitReadExclusive -> xactReplyReadExclusive,
|
||||
xactInitReadUncached -> xactReplyReadUncached,
|
||||
xactInitWriteUncached -> xactReplyWriteUncached
|
||||
xactInitWriteUncached -> xactReplyWriteUncached,
|
||||
xactInitReadWordUncached -> xactReplyReadWordUncached,
|
||||
xactInitWriteWordUncached -> xactReplyWriteWordUncached,
|
||||
xactInitAtomicUncached -> xactReplyAtomicUncached
|
||||
))
|
||||
}
|
||||
|
||||
@ -661,7 +746,10 @@ class MESICoherence extends CoherencePolicyWithUncached {
|
||||
xactInitReadShared -> probeReqDowngrade,
|
||||
xactInitReadExclusive -> probeReqInvalidate,
|
||||
xactInitReadUncached -> probeReqCopy,
|
||||
xactInitWriteUncached -> probeReqInvalidate
|
||||
xactInitWriteUncached -> probeReqInvalidate,
|
||||
xactInitReadWordUncached -> probeReqCopy,
|
||||
xactInitWriteWordUncached -> probeReqInvalidate,
|
||||
xactInitAtomicUncached -> probeReqInvalidate
|
||||
))
|
||||
}
|
||||
|
||||
|
||||
@ -200,6 +200,9 @@ object Constants
|
||||
val GLOBAL_XACT_ID_BITS = log2Up(NGLOBAL_XACTS)
|
||||
|
||||
val X_INIT_TYPE_MAX_BITS = 2
|
||||
val X_INIT_WRITE_MASK_BITS = OFFSET_BITS
|
||||
val X_INIT_SUBWORD_ADDR_BITS = log2Up(OFFSET_BITS)
|
||||
val X_INIT_ATOMIC_OP_BITS = 4
|
||||
val X_REP_TYPE_MAX_BITS = 3
|
||||
val P_REQ_TYPE_MAX_BITS = 2
|
||||
val P_REP_TYPE_MAX_BITS = 3
|
||||
|
||||
@ -176,8 +176,8 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
|
||||
mem_req_data = Cat(packet_ram(idx), mem_req_data)
|
||||
}
|
||||
x_init.io.enq.valid := state === state_mem_req
|
||||
x_init.io.enq.bits.x_type := Mux(cmd === cmd_writemem, co.getTransactionInitTypeOnUncachedWrite, co.getTransactionInitTypeOnUncachedRead)
|
||||
x_init.io.enq.bits.address := addr.toUFix >> UFix(OFFSET_BITS-3)
|
||||
val init_addr = addr.toUFix >> UFix(OFFSET_BITS-3)
|
||||
x_init.io.enq.bits := Mux(cmd === cmd_writemem, co.getUncachedWriteTransactionInit(init_addr, UFix(0)), co.getUncachedReadTransactionInit(init_addr, UFix(0)))
|
||||
io.mem.xact_init <> x_init.io.deq
|
||||
io.mem.xact_init_data.valid:= state === state_mem_wdata
|
||||
io.mem.xact_init_data.bits.data := mem_req_data
|
||||
|
||||
@ -136,8 +136,7 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten
|
||||
rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || tag_hit);
|
||||
io.cpu.resp_data := data_mux.io.out
|
||||
io.mem.xact_init.valid := (state === s_request) && finish_q.io.enq.ready
|
||||
io.mem.xact_init.bits.x_type := co.getTransactionInitTypeOnUncachedRead
|
||||
io.mem.xact_init.bits.address := r_cpu_miss_addr(tagmsb,indexlsb).toUFix
|
||||
io.mem.xact_init.bits := co.getUncachedReadTransactionInit(r_cpu_miss_addr(tagmsb,indexlsb).toUFix, UFix(0))
|
||||
io.mem.xact_finish <> finish_q.io.deq
|
||||
|
||||
// control state machine
|
||||
|
||||
@ -282,7 +282,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
|
||||
|
||||
io.mem_req.valid := (state === s_refill_req) && !flush
|
||||
io.mem_req.bits.x_type := xacx_type
|
||||
io.mem_req.bits.address := Cat(req.tag, req.idx).toUFix
|
||||
io.mem_req.bits.addr := Cat(req.tag, req.idx).toUFix
|
||||
io.mem_req.bits.tile_xact_id := Bits(id)
|
||||
io.mem_finish <> finish_q.io.deq
|
||||
|
||||
@ -475,7 +475,7 @@ class WritebackUnit(co: CoherencePolicy) extends Component {
|
||||
|
||||
io.mem_req.valid := valid && !cmd_sent
|
||||
io.mem_req.bits.x_type := co.getTransactionInitTypeOnWriteback()
|
||||
io.mem_req.bits.address := Cat(req.tag, req.idx).toUFix
|
||||
io.mem_req.bits.addr := Cat(req.tag, req.idx).toUFix
|
||||
io.mem_req.bits.tile_xact_id := req.tile_xact_id
|
||||
io.mem_req_data.valid := data_req_fired && !is_probe
|
||||
io.mem_req_data.bits.data := io.data_resp
|
||||
@ -492,7 +492,7 @@ class ProbeUnit(co: CoherencePolicy) extends Component {
|
||||
val wb_req = (new FIFOIO) { new WritebackReq }
|
||||
val tag_match_way_oh = Bits(INPUT, NWAYS)
|
||||
val line_state = UFix(INPUT, 2)
|
||||
val address = Bits(OUTPUT, PADDR_BITS-OFFSET_BITS)
|
||||
val addr = Bits(OUTPUT, PADDR_BITS-OFFSET_BITS)
|
||||
}
|
||||
|
||||
val s_reset :: s_invalid :: s_meta_req :: s_meta_resp :: s_mshr_req :: s_probe_rep :: s_writeback_req :: s_writeback_resp :: Nil = Enum(8) { UFix() }
|
||||
@ -535,16 +535,16 @@ class ProbeUnit(co: CoherencePolicy) extends Component {
|
||||
io.meta_req.valid := state === s_meta_req || state === s_meta_resp || state === s_mshr_req || state === s_probe_rep && hit
|
||||
io.meta_req.bits.way_en := Mux(state === s_probe_rep, way_oh, ~UFix(0, NWAYS))
|
||||
io.meta_req.bits.rw := state === s_probe_rep
|
||||
io.meta_req.bits.idx := req.address
|
||||
io.meta_req.bits.idx := req.addr
|
||||
io.meta_req.bits.data.state := co.newStateOnProbeRequest(req, line_state)
|
||||
io.meta_req.bits.data.tag := req.address >> UFix(IDX_BITS)
|
||||
io.meta_req.bits.data.tag := req.addr >> UFix(IDX_BITS)
|
||||
io.mshr_req.valid := state === s_meta_resp || state === s_mshr_req
|
||||
io.address := req.address
|
||||
io.addr := req.addr
|
||||
|
||||
io.wb_req.valid := state === s_writeback_req
|
||||
io.wb_req.bits.way_oh := way_oh
|
||||
io.wb_req.bits.idx := req.address
|
||||
io.wb_req.bits.tag := req.address >> UFix(IDX_BITS)
|
||||
io.wb_req.bits.idx := req.addr
|
||||
io.wb_req.bits.tag := req.addr >> UFix(IDX_BITS)
|
||||
}
|
||||
|
||||
class FlushUnit(lines: Int, co: CoherencePolicy) extends Component {
|
||||
@ -860,7 +860,7 @@ class HellaCache(co: CoherencePolicy) extends Component {
|
||||
meta_arb.io.in(3).bits.rw := Bool(false)
|
||||
meta_arb.io.in(3).bits.way_en := ~UFix(0, NWAYS)
|
||||
val early_tag_nack = !meta_arb.io.in(3).ready
|
||||
val cpu_req_ppn = Mux(prober.io.mshr_req.valid, prober.io.address >> UFix(PGIDX_BITS-OFFSET_BITS), io.cpu.req.bits.ppn)
|
||||
val cpu_req_ppn = Mux(prober.io.mshr_req.valid, prober.io.addr >> UFix(PGIDX_BITS-OFFSET_BITS), io.cpu.req.bits.ppn)
|
||||
val cpu_req_tag = Cat(cpu_req_ppn, r_cpu_req_idx)(tagmsb,taglsb)
|
||||
val tag_match_arr = (0 until NWAYS).map( w => co.isValid(meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
|
||||
val tag_match = Cat(Bits(0),tag_match_arr:_*).orR
|
||||
|
||||
@ -3,14 +3,17 @@ package rocket
|
||||
import Chisel._
|
||||
import Constants._
|
||||
|
||||
class PhysicalAddress extends Bundle {
|
||||
val addr = UFix(width = PADDR_BITS - OFFSET_BITS)
|
||||
}
|
||||
|
||||
class MemData extends Bundle {
|
||||
val data = Bits(width = MEM_DATA_BITS)
|
||||
}
|
||||
|
||||
class MemReqCmd() extends Bundle
|
||||
class MemReqCmd() extends PhysicalAddress
|
||||
{
|
||||
val rw = Bool()
|
||||
val addr = UFix(width = PADDR_BITS - OFFSET_BITS)
|
||||
val tag = Bits(width = MEM_TAG_BITS)
|
||||
}
|
||||
|
||||
@ -165,7 +168,7 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
|
||||
io.probe_req.valid := Bool(false)
|
||||
io.probe_req.bits.p_type := co.getProbeRequestType(x_type_, UFix(0))
|
||||
io.probe_req.bits.global_xact_id := UFix(id)
|
||||
io.probe_req.bits.address := addr_
|
||||
io.probe_req.bits.addr := addr_
|
||||
io.push_p_req := Bits(0, width = ntiles)
|
||||
io.pop_p_rep := Bits(0, width = ntiles)
|
||||
io.pop_p_rep_data := Bits(0, width = ntiles)
|
||||
@ -178,7 +181,7 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
|
||||
switch (state) {
|
||||
is(s_idle) {
|
||||
when( io.alloc_req.valid && io.can_alloc ) {
|
||||
addr_ := io.alloc_req.bits.xact_init.address
|
||||
addr_ := io.alloc_req.bits.xact_init.addr
|
||||
x_type_ := io.alloc_req.bits.xact_init.x_type
|
||||
init_tile_id_ := io.alloc_req.bits.tile_id
|
||||
tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id
|
||||
@ -272,7 +275,7 @@ class CoherenceHubNull(co: ThreeStateIncoherence) extends CoherenceHub(1, co)
|
||||
io.mem.req_cmd.valid := x_init.valid && !(is_write && io.mem.resp.valid)
|
||||
io.mem.req_cmd.bits.rw := is_write
|
||||
io.mem.req_cmd.bits.tag := x_init.bits.tile_xact_id
|
||||
io.mem.req_cmd.bits.addr := x_init.bits.address
|
||||
io.mem.req_cmd.bits.addr := x_init.bits.addr
|
||||
io.mem.req_data <> io.tiles(0).xact_init_data
|
||||
|
||||
val x_rep = io.tiles(0).xact_rep
|
||||
@ -432,7 +435,7 @@ class CoherenceHubBroadcast(ntiles: Int, co: CoherencePolicy) extends CoherenceH
|
||||
val conflicts = Vec(NGLOBAL_XACTS) { Bool() }
|
||||
for( i <- 0 until NGLOBAL_XACTS) {
|
||||
val t = trackerList(i).io
|
||||
conflicts(i) := t.busy && x_init.valid && co.isCoherenceConflict(t.addr, x_init.bits.address)
|
||||
conflicts(i) := t.busy && x_init.valid && co.isCoherenceConflict(t.addr, x_init.bits.addr)
|
||||
}
|
||||
x_abort.bits.tile_xact_id := x_init.bits.tile_xact_id
|
||||
want_to_abort_arr(j) := x_init.valid && (conflicts.toBits.orR || busy_arr.toBits.andR || (!x_init_data_dep_list(j).io.enq.ready && co.messageHasData(x_init.bits)))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user