riscv/rocket-chip
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uncore and rocket changes for new xact types

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This commit is contained in:
Henry Cook
2012-09-27 16:46:36 -07:00
parent d9cb96c0ae
commit b9a9664de5
6 changed files with 165 additions and 72 deletions
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3
rocket/src/main/scala/icache.scala
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@ -136,8 +136,7 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten
rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || tag_hit);
io.cpu.resp_data := data_mux.io.out
io.mem.xact_init.valid := (state === s_request) && finish_q.io.enq.ready
io.mem.xact_init.bits.x_type := co.getTransactionInitTypeOnUncachedRead
io.mem.xact_init.bits.address := r_cpu_miss_addr(tagmsb,indexlsb).toUFix
io.mem.xact_init.bits := co.getUncachedReadTransactionInit(r_cpu_miss_addr(tagmsb,indexlsb).toUFix, UFix(0))
io.mem.xact_finish <> finish_q.io.deq
// control state machine