riscv/rocket-chip
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diplomacy: API beautification

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This commit is contained in:
Wesley W. Terpstra
2017-09-15 14:44:07 -07:00
parent 9217baf9d4
commit b9a2e4c243
17 changed files with 38 additions and 25 deletions
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3
src/main/scala/tile/Interrupts.scala
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@@ -56,6 +56,7 @@ trait HasExternalInterruptsModule {
val core_ips = core.lip
(async_ips ++ periph_ips ++ seip ++ core_ips).zip(outer.intNode.in(0)._1).foreach { case(c, i) => c := i }
val (interrupts, _) = outer.intNode.in(0)
(async_ips ++ periph_ips ++ seip ++ core_ips).zip(interrupts).foreach { case(c, i) => c := i }
}
}

4
src/main/scala/tile/RocketTile.scala
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@@ -82,7 +82,7 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
}))
// Find all the caches
val outer = masterNode.out.map(_._2)
val outer = masterNode.edges.out
.flatMap(_.manager.managers)
.filter(_.supportsAcquireB)
.flatMap(_.resources.headOption)
@@ -115,7 +115,7 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
Resource(cpuDevice, "reg").bind(ResourceInt(BigInt(hartid)))
Resource(intcDevice, "reg").bind(ResourceInt(BigInt(hartid)))
intNode.in.flatMap(_._2.source.sources).map { case s =>
intNode.edges.in.flatMap(_.source.sources).map { case s =>
for (i <- s.range.start until s.range.end) {
csrIntMap.lift(i).foreach { j =>
s.resources.foreach { r =>