riscv/rocket-chip
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diplomacy: API beautification

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This commit is contained in:
Wesley W. Terpstra
2017-09-15 14:44:07 -07:00
parent 9217baf9d4
commit b9a2e4c243
17 changed files with 38 additions and 25 deletions
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2
src/main/scala/rocket/PTW.scala
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@ -283,7 +283,7 @@ trait CanHavePTW extends HasHellaCache {
trait CanHavePTWModule extends HasHellaCacheModule {
val outer: CanHavePTW
val ptwPorts = ListBuffer(outer.dcache.module.io.ptw)
val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.out(0)._2, outer.p))
val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p))
if (outer.usingPTW)
dcachePorts += ptw.io.mem
}