riscv/rocket-chip
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diplomacy: API beautification

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Wesley W. Terpstra committed 2017-09-22 15:01:42 -07:00
1 parent 9217baf9d4
commit b9a2e4c243
17 files changed
+38 -25
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src/main/scala/rocket/Frontend.scala
+1 -1
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@@ -75,7 +75,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
with HasCoreParameters
with HasL1ICacheParameters {
val io = IO(new FrontendBundle(outer))
implicit val edge = outer.masterNode.out(0)._2
implicit val edge = outer.masterNode.edges.out(0)
val icache = outer.icache.module
require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes)