riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

diplomacy: API beautification

Browse Source
This commit is contained in:
Wesley W. Terpstra
2017-09-15 14:44:07 -07:00
parent 9217baf9d4
commit b9a2e4c243
17 changed files with 38 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/rocket/Frontend.scala
View File

@ -75,7 +75,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
with HasCoreParameters
with HasL1ICacheParameters {
val io = IO(new FrontendBundle(outer))
implicit val edge = outer.masterNode.out(0)._2
implicit val edge = outer.masterNode.edges.out(0)
val icache = outer.icache.module
require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes)