riscv/rocket-chip
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diplomacy: API beautification

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This commit is contained in:
Wesley W. Terpstra
2017-09-15 14:44:07 -07:00
parent 9217baf9d4
commit b9a2e4c243
17 changed files with 38 additions and 25 deletions
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2
src/main/scala/rocket/Frontend.scala
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@ -75,7 +75,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
with HasCoreParameters
with HasL1ICacheParameters {
val io = IO(new FrontendBundle(outer))
implicit val edge = outer.masterNode.out(0)._2
implicit val edge = outer.masterNode.edges.out(0)
val icache = outer.icache.module
require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes)

4
src/main/scala/rocket/HellaCache.scala
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@ -181,8 +181,8 @@ class HellaCacheBundle(outer: HellaCache)(implicit p: Parameters) extends CoreBu
class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
with HasL1HellaCacheParameters {
implicit val edge = outer.node.out(0)._2
val tl_out = outer.node.out(0)._1
implicit val edge = outer.node.edges.out(0)
val (tl_out, _) = outer.node.out(0)
val io = IO(new HellaCacheBundle(outer))
private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allUncacheable)

2
src/main/scala/rocket/ICache.scala
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@ -109,6 +109,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
val io = IO(new ICacheBundle(outer))
val (tl_out, edge_out) = outer.masterNode.out(0)
// Option.unzip does not exist :-(
// val (tl_in, edge_in) = outer.slaveNode.map(_.in(0)).unzip
val tl_in = outer.slaveNode.map(_.in(0)._1)
val edge_in = outer.slaveNode.map(_.in(0)._2)

2
src/main/scala/rocket/PTW.scala
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@ -283,7 +283,7 @@ trait CanHavePTW extends HasHellaCache {
trait CanHavePTWModule extends HasHellaCacheModule {
val outer: CanHavePTW
val ptwPorts = ListBuffer(outer.dcache.module.io.ptw)
val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.out(0)._2, outer.p))
val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p))
if (outer.usingPTW)
dcachePorts += ptw.io.mem
}

2
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -127,7 +127,7 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
}
def findScratchpadFromICache: Option[AddressSet] = scratch.map { s =>
val finalNode = frontend.masterNode.out.head._2.manager.managers.find(_.nodePath.last == s.node)
val finalNode = frontend.masterNode.edges.out.head.manager.managers.find(_.nodePath.last == s.node)
require (finalNode.isDefined, "Could not find the scratch pad; not reachable via icache?")
require (finalNode.get.address.size == 1, "Scratchpad address space was fragmented!")
finalNode.get.address(0)