riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

diplomacy: API beautification

Browse Source
This commit is contained in:
Wesley W. Terpstra
2017-09-15 14:44:07 -07:00
parent 9217baf9d4
commit b9a2e4c243
17 changed files with 38 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/coreplex/SystemBus.scala
View File

@ -22,7 +22,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
private val master_splitter = LazyModule(new TLSplitter) // Allows cycle-free connection to external networks
master_splitter.suggestName(s"${busName}_master_TLSplitter")
inwardNode :=* master_splitter.node
def busView = master_splitter.node.in.head._2
def busView = master_splitter.node.edges.in.head
protected def inwardSplitNode: TLInwardNode = master_splitter.node
protected def outwardSplitNode: TLOutwardNode = master_splitter.node