riscv/rocket-chip
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diplomacy: API beautification

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Wesley W. Terpstra committed 2017-09-22 15:01:42 -07:00
1 parent 9217baf9d4
commit b9a2e4c243
17 files changed
+38 -25
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src/main/scala/coreplex/SystemBus.scala
+1 -1
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@@ -22,7 +22,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
private val master_splitter = LazyModule(new TLSplitter) // Allows cycle-free connection to external networks
master_splitter.suggestName(s"${busName}_master_TLSplitter")
inwardNode :=* master_splitter.node
def busView = master_splitter.node.in.head._2
def busView = master_splitter.node.edges.in.head
protected def inwardSplitNode: TLInwardNode = master_splitter.node
protected def outwardSplitNode: TLOutwardNode = master_splitter.node