PLIC: converted to TL2
This commit is contained in:
Wesley W. Terpstra
parent
bddfa4d69b
commit
b99662796d
@ -51,13 +51,21 @@ case class CoreplexConfig(
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abstract class BaseCoreplex(c: CoreplexConfig)(implicit val p: Parameters) extends LazyModule with HasCoreplexParameters {
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val debugLegacy = LazyModule(new TLLegacy()(outerMMIOParams))
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val debugModule = LazyModule(new TLDebugModule())
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debugModule.node :=
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val debug = LazyModule(new TLDebugModule())
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debug.node :=
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TLHintHandler()(
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TLBuffer()(
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TLFragmenter(p(XLen)/8, debugLegacy.tlDataBeats * debugLegacy.tlDataBytes)(
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TLWidthWidget(debugLegacy.tlDataBytes)(debugLegacy.node))))
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val plicLegacy = LazyModule(new TLLegacy()(outerMMIOParams))
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val plic = LazyModule(new TLPLIC(c.plicKey))
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plic.node :=
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TLHintHandler()(
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TLBuffer()(
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TLFragmenter(p(XLen)/8, plicLegacy.tlDataBeats * plicLegacy.tlDataBytes)(
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TLWidthWidget(plicLegacy.tlDataBytes)(plicLegacy.node))))
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}
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abstract class BaseCoreplexBundle(val c: CoreplexConfig)(implicit val p: Parameters) extends Bundle with HasCoreplexParameters {
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@ -142,23 +150,22 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
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val cBus = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap))
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cBus.io.in.head <> mmio
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val plic = Module(new PLIC(c.plicKey))
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plic.io.tl <> cBus.port("cbus:plic")
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outer.plicLegacy.module.io.legacy <> cBus.port("cbus:plic")
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for (i <- 0 until io.interrupts.size) {
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val gateway = Module(new LevelGateway)
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gateway.io.interrupt := io.interrupts(i)
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plic.io.devices(i) <> gateway.io.plic
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outer.plic.module.io.devices(i) <> gateway.io.plic
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}
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outer.debugLegacy.module.io.legacy <> cBus.port("cbus:debug")
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outer.debugModule.module.io.db <> io.debug
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outer.debug.module.io.db <> io.debug
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// connect coreplex-internal interrupts to tiles
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for ((tile, i) <- (uncoreTileIOs zipWithIndex)) {
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tile.interrupts <> io.clint(i)
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tile.interrupts.meip := plic.io.harts(plic.cfg.context(i, 'M'))
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tile.interrupts.seip.foreach(_ := plic.io.harts(plic.cfg.context(i, 'S')))
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tile.interrupts.debug := outer.debugModule.module.io.debugInterrupts(i)
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tile.interrupts.meip := outer.plic.module.io.harts(c.plicKey.context(i, 'M'))
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tile.interrupts.seip.foreach(_ := outer.plic.module.io.harts(c.plicKey.context(i, 'S')))
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tile.interrupts.debug := outer.debug.module.io.debugInterrupts(i)
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tile.hartid := UInt(i)
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tile.resetVector := io.resetVector
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}
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@ -6,7 +6,8 @@ import Chisel._
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import Chisel.ImplicitConversions._
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import junctions._
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import uncore.tilelink._
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import regmapper._
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import uncore.tilelink2._
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import cde.Parameters
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class GatewayPLICIO extends Bundle {
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@ -27,7 +28,7 @@ class LevelGateway extends Module {
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io.plic.valid := io.interrupt && !inFlight
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}
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case class PLICConfig(nHartsIn: Int, supervisor: Boolean, nDevices: Int, nPriorities: Int) {
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case class PLICConfig(nHartsIn: Int, supervisor: Boolean, nDevices: Int, nPriorities: Int, address: BigInt = 0xC000000) {
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def contextsPerHart = if (supervisor) 2 else 1
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def nHarts = contextsPerHart * nHartsIn
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def context(i: Int, mode: Char) = mode match {
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@ -41,6 +42,7 @@ case class PLICConfig(nHartsIn: Int, supervisor: Boolean, nDevices: Int, nPriori
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def maxDevices = 1023
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def maxHarts = 15872
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def priorityBase = 0x0
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def pendingBase = 0x1000
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def enableBase = 0x2000
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def hartBase = 0x200000
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@ -56,16 +58,20 @@ case class PLICConfig(nHartsIn: Int, supervisor: Boolean, nDevices: Int, nPriori
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require(nPriorities >= 0 && nPriorities <= nDevices)
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}
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/** Platform-Level Interrupt Controller */
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class PLIC(val cfg: PLICConfig)(implicit val p: Parameters) extends Module
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with HasTileLinkParameters
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with HasAddrMapParameters {
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val io = new Bundle {
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trait HasPLICParamters {
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val params: (PLICConfig, Parameters)
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val cfg = params._1
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implicit val p = params._2
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}
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trait PLICBundle extends Bundle with HasPLICParamters {
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val devices = Vec(cfg.nDevices, new GatewayPLICIO).flip
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val harts = Vec(cfg.nHarts, Bool()).asOutput
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val tl = new ClientUncachedTileLinkIO().flip
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}
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trait PLICModule extends Module with HasRegMap with HasPLICParamters {
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val io: PLICBundle
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val priority =
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if (cfg.nPriorities > 0) Reg(Vec(cfg.nDevices+1, UInt(width=log2Up(cfg.nPriorities+1))))
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else Wire(init=Vec.fill(cfg.nDevices+1)(UInt(1)))
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@ -87,7 +93,7 @@ class PLIC(val cfg: PLICConfig)(implicit val p: Parameters) extends Module
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val lMax = findMax(x take half)
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val rMax = findMax(x drop half)
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val useLeft = lMax._1 >= rMax._1
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(Mux(useLeft, lMax._1, rMax._1), Mux(useLeft, lMax._2, UInt(half) + rMax._2))
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(Mux(useLeft, lMax._1, rMax._1), Mux(useLeft, lMax._2, UInt(half) | rMax._2))
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} else (x.head, UInt(0))
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}
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@ -102,86 +108,45 @@ class PLIC(val cfg: PLICConfig)(implicit val p: Parameters) extends Module
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io.harts(hart) := Reg(next = maxPri) > Cat(UInt(1), threshold(hart))
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}
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val acq = Queue(io.tl.acquire, 1)
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val read = acq.fire() && acq.bits.isBuiltInType(Acquire.getType)
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val write = acq.fire() && acq.bits.isBuiltInType(Acquire.putType)
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assert(!acq.fire() || read || write, "unsupported PLIC operation")
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val addr = acq.bits.full_addr()(log2Up(cfg.size)-1,0)
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def priorityRegField(x: UInt) = if (cfg.nPriorities > 0) RegField(32, x) else RegField.r(32, x)
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val piorityRegFields = Seq(cfg.priorityBase -> priority.map(p => priorityRegField(p)))
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val pendingRegFields = Seq(cfg.pendingBase -> pending .map(b => RegField.r(1, b)))
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val claimant =
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if (cfg.nHarts == 1) UInt(0)
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else (addr - cfg.hartBase)(log2Up(cfg.hartOffset(cfg.nHarts))-1,log2Up(cfg.hartOffset(1)))
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val hart = Wire(init = claimant)
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val myMaxDev = maxDevs(claimant)
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val myEnables = enables(hart)
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val rdata = Wire(init = UInt(0, tlDataBits))
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val masked_wdata = (acq.bits.data & acq.bits.full_wmask()) | (rdata & ~acq.bits.full_wmask())
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val enableRegFields = enables.zipWithIndex.map { case (e, i) =>
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cfg.enableBase + cfg.enableOffset(i) -> e.map(b => RegField(1, b))
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}
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if (cfg.nDevices > 0) when (addr >= cfg.hartBase) {
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val word =
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if (tlDataBytes > cfg.claimOffset) UInt(0)
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else addr(log2Up(cfg.claimOffset),log2Up(tlDataBytes))
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rdata := Cat(myMaxDev, UInt(0, 8*cfg.priorityBytes-threshold(0).getWidth), threshold(claimant)) >> (word * tlDataBits)
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val hartRegFields = Seq.tabulate(cfg.nHarts) { i =>
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cfg.hartBase + cfg.hartOffset(i) -> Seq(
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priorityRegField(threshold(i)),
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RegField(32,
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RegReadFn { valid =>
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when (valid) {
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pending(maxDevs(i)) := Bool(false)
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maxDevs(i) := UInt(0) // flush pipeline
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}
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(Bool(true), maxDevs(i))
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},
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RegWriteFn { (valid, data) =>
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when (valid && enables(i)(data)) {
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io.devices(data - UInt(1)).complete := Bool(true)
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}
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Bool(true)
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}
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)
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)
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}
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when (read && addr(log2Ceil(cfg.claimOffset))) {
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pending(myMaxDev) := false
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}
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when (write) {
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when (if (tlDataBytes > cfg.claimOffset) acq.bits.wmask()(cfg.claimOffset) else addr(log2Ceil(cfg.claimOffset))) {
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val dev = (acq.bits.data >> ((8 * cfg.claimOffset) % tlDataBits))(log2Up(pending.size)-1,0)
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when (myEnables(dev)) { io.devices(dev-1).complete := true }
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}.otherwise {
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if (cfg.nPriorities > 0) threshold(claimant) := acq.bits.data
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}
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}
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}.elsewhen (addr >= cfg.enableBase) {
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val enableHart =
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if (cfg.nHarts > 1) (addr - cfg.enableBase)(log2Up(cfg.enableOffset(cfg.nHarts))-1,log2Up(cfg.enableOffset(1)))
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else UInt(0)
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hart := enableHart
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val word =
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if (tlDataBits >= myEnables.size) UInt(0)
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else addr(log2Ceil((myEnables.size-1)/tlDataBits+1) + tlByteAddrBits - 1, tlByteAddrBits)
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for (i <- 0 until myEnables.size by tlDataBits) {
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when (word === i/tlDataBits) {
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rdata := Cat(myEnables.slice(i, i + tlDataBits).reverse)
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for (j <- 0 until (tlDataBits min (myEnables.size - i))) {
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when (write) { enables(enableHart)(i+j) := masked_wdata(j) }
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}
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}
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}
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}.elsewhen (addr >= cfg.pendingBase) {
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val word =
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if (tlDataBytes >= pending.size) UInt(0)
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else addr(log2Up(pending.size)-1,log2Up(tlDataBytes))
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rdata := pending.asUInt >> (word * tlDataBits)
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}.otherwise {
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val regsPerBeat = tlDataBytes >> log2Up(cfg.priorityBytes)
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val word =
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if (regsPerBeat >= priority.size) UInt(0)
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else addr(log2Up(priority.size*cfg.priorityBytes)-1,log2Up(tlDataBytes))
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for (i <- 0 until priority.size by regsPerBeat) {
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when (word === i/regsPerBeat) {
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rdata := Cat(priority.slice(i, i + regsPerBeat).map(p => Cat(UInt(0, 8*cfg.priorityBytes-p.getWidth), p)).reverse)
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for (j <- 0 until (regsPerBeat min (priority.size - i))) {
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if (cfg.nPriorities > 0) when (write) { priority(i+j) := masked_wdata >> (j * 8 * cfg.priorityBytes) }
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}
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}
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}
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}
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regmap((piorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*)
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priority(0) := 0
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pending(0) := false
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for (e <- enables)
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e(0) := false
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io.tl.grant.valid := acq.valid
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acq.ready := io.tl.grant.ready
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io.tl.grant.bits := Grant(
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is_builtin_type = Bool(true),
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g_type = acq.bits.getBuiltInGrantType(),
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client_xact_id = acq.bits.client_xact_id,
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manager_xact_id = UInt(0),
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addr_beat = UInt(0),
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data = rdata)
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}
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/** Platform-Level Interrupt Controller */
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class TLPLIC(c: PLICConfig)(implicit val p: Parameters)
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extends TLRegisterRouter(c.address, size = c.size, beatBytes = p(rocket.XLen)/8, undefZero = false)(
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new TLRegBundle((c, p), _) with PLICBundle)(
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new TLRegModule((c, p), _, _) with PLICModule)
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