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debug: redirect DMI NOPs to CONTROL register so things don't hang during reset

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Megan Wachs 2017-04-04 13:22:51 -07:00 committed by Andrew Waterman
parent eef05cc1fc
commit b94f1f15b0
1 changed files with 8 additions and 3 deletions
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11
src/main/scala/uncore/devices/debug/Debug.scala
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@ -1141,9 +1141,14 @@ class DMIToTL(implicit p: Parameters) extends LazyModule {
val (_, gbits) = edge.Get(src, addr, size) val (_, gbits) = edge.Get(src, addr, size)
val (_, pfbits) = edge.Put(src, addr, size, io.dmi.req.bits.data) val (_, pfbits) = edge.Put(src, addr, size, io.dmi.req.bits.data)
// This is just used for the DMI's NOP. TODO: Consider whether to send this
// across TL at all or just respond immediately. // Note we force DMI NOPs to go to CONTROL register because
val (_, nbits) = edge.Put(src, addr, size, io.dmi.req.bits.data, mask = 0.U) // Inner may be in reset / not have a clock,
// so we force address to be the one that goes to Outer.
// Besides, for a NOP we don't really need to pay the penalty to go
// across the CDC.
val (_, nbits) = edge.Put(src, toAddress = (DMI_RegAddrs.DMI_DMCONTROL << 2).U, size, data=0.U, mask = 0.U)
when (io.dmi.req.bits.op === DMIConsts.dmi_OP_WRITE) { tl.a.bits := pfbits when (io.dmi.req.bits.op === DMIConsts.dmi_OP_WRITE) { tl.a.bits := pfbits
}.elsewhen (io.dmi.req.bits.op === DMIConsts.dmi_OP_READ) { tl.a.bits := gbits }.elsewhen (io.dmi.req.bits.op === DMIConsts.dmi_OP_READ) { tl.a.bits := gbits