diff --git a/src/main/scala/uncore/devices/debug/Debug.scala b/src/main/scala/uncore/devices/debug/Debug.scala
index a7472ec4..3449fef1 100644
--- a/src/main/scala/uncore/devices/debug/Debug.scala
+++ b/src/main/scala/uncore/devices/debug/Debug.scala
@@ -1141,9 +1141,14 @@ class DMIToTL(implicit p: Parameters) extends LazyModule {
 
     val (_,  gbits) = edge.Get(src, addr, size)
     val (_, pfbits) = edge.Put(src, addr, size, io.dmi.req.bits.data)
-    // This is just used for the DMI's NOP. TODO: Consider whether to send this
-    // across TL at all or just respond immediately.
-    val (_, nbits)  = edge.Put(src, addr, size, io.dmi.req.bits.data, mask = 0.U)
+
+    // Note we force DMI NOPs to go to CONTROL register because
+    // Inner  may be in reset / not have a clock,
+    // so we force address to be the one that goes to Outer.
+    // Besides, for a NOP we don't really need to pay the penalty to go
+    // across the CDC.
+
+    val (_, nbits)  = edge.Put(src, toAddress = (DMI_RegAddrs.DMI_DMCONTROL << 2).U, size, data=0.U, mask = 0.U)
 
     when (io.dmi.req.bits.op === DMIConsts.dmi_OP_WRITE)       { tl.a.bits := pfbits
     }.elsewhen  (io.dmi.req.bits.op === DMIConsts.dmi_OP_READ) { tl.a.bits := gbits