riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

config: use Field defaults over Config defaults

Browse Source 
Also rename some keys that had the same class name as their value's class name.
This commit is contained in:
Henry Cook
2017-09-08 18:33:44 -07:00
parent a7540d35b7
commit b86f4b9bb7
18 changed files with 57 additions and 68 deletions
Download Patch File Download Diff File Expand all files Collapse all files

48
src/main/scala/coreplex/Configs.scala
View File

@ -16,25 +16,17 @@ import freechips.rocketchip.util._
class BaseCoreplexConfig extends Config ((site, here, up) => {
// Tile parameters
case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
case ASIdBits => 0
case XLen => 64 // Applies to all cores
case MaxHartIdBits => log2Up(site(RocketTilesKey).size)
case BuildCore => (p: Parameters) => new Rocket()(p)
case RocketTilesKey => Nil // Will be added by partial configs found below
// Interconnect parameters
case RocketCrossing => SynchronousCrossing()
case BroadcastParams => BroadcastParams()
case BankedL2Params => BankedL2Params()
case SystemBusParams => SystemBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
case PeripheryBusParams => PeripheryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
case MemoryBusParams => MemoryBusParams(beatBytes = 8, blockBytes = site(CacheBlockBytes))
case CacheBlockBytes => 64
// Device parameters
case SystemBusKey => SystemBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
case PeripheryBusKey => PeripheryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
case MemoryBusKey => MemoryBusParams(beatBytes = 8, blockBytes = site(CacheBlockBytes))
// Additional device Parameters
case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)))
case BootROMParams => BootROMParams(contentFileName = "./bootrom/bootrom.img")
case DebugModuleParams => DefaultDebugModuleParams(site(XLen))
case PLICParams => PLICParams()
case ClintParams => ClintParams()
case DTSTimebase => BigInt(1000000) // 1 MHz
case TLBusDelayProbability => 0.0
})
/* Composable partial function Configs to set individual parameters */
@ -47,11 +39,11 @@ class WithNBigCores(n: Int) extends Config((site, here, up) => {
mulEarlyOut = true,
divEarlyOut = true))),
dcache = Some(DCacheParams(
rowBits = site(SystemBusParams).beatBits,
rowBits = site(SystemBusKey).beatBits,
nMSHRs = 0,
blockBytes = site(CacheBlockBytes))),
icache = Some(ICacheParams(
rowBits = site(SystemBusParams).beatBits,
rowBits = site(SystemBusKey).beatBits,
blockBytes = site(CacheBlockBytes))))
List.fill(n)(big) ++ up(RocketTilesKey, site)
}
@ -63,14 +55,14 @@ class WithNSmallCores(n: Int) extends Config((site, here, up) => {
core = RocketCoreParams(useVM = false, fpu = None),
btb = None,
dcache = Some(DCacheParams(
rowBits = site(SystemBusParams).beatBits,
rowBits = site(SystemBusKey).beatBits,
nSets = 64,
nWays = 1,
nTLBEntries = 4,
nMSHRs = 0,
blockBytes = site(CacheBlockBytes))),
icache = Some(ICacheParams(
rowBits = site(SystemBusParams).beatBits,
rowBits = site(SystemBusKey).beatBits,
nSets = 64,
nWays = 1,
nTLBEntries = 4,
@ -89,7 +81,7 @@ class WithNTinyCores(n: Int) extends Config((site, here, up) => {
mulDiv = Some(MulDivParams(mulUnroll = 8))),
btb = None,
dcache = Some(DCacheParams(
rowBits = site(SystemBusParams).beatBits,
rowBits = site(SystemBusKey).beatBits,
nSets = 256, // 16Kb scratchpad
nWays = 1,
nTLBEntries = 4,
@ -97,7 +89,7 @@ class WithNTinyCores(n: Int) extends Config((site, here, up) => {
blockBytes = site(CacheBlockBytes),
scratch = Some(0x80000000L))),
icache = Some(ICacheParams(
rowBits = site(SystemBusParams).beatBits,
rowBits = site(SystemBusKey).beatBits,
nSets = 64,
nWays = 1,
nTLBEntries = 4,
@ -107,11 +99,11 @@ class WithNTinyCores(n: Int) extends Config((site, here, up) => {
})
class WithNBanksPerMemChannel(n: Int) extends Config((site, here, up) => {
case BankedL2Params => up(BankedL2Params, site).copy(nBanksPerChannel = n)
case BankedL2Key => up(BankedL2Key, site).copy(nBanksPerChannel = n)
})
class WithNTrackersPerBank(n: Int) extends Config((site, here, up) => {
case BroadcastParams => up(BroadcastParams, site).copy(nTrackers = n)
case BroadcastKey => up(BroadcastKey, site).copy(nTrackers = n)
})
// This is the number of icache sets for all Rocket tiles
@ -143,7 +135,7 @@ class WithCacheBlockBytes(linesize: Int) extends Config((site, here, up) => {
})
class WithBufferlessBroadcastHub extends Config((site, here, up) => {
case BroadcastParams => up(BroadcastParams, site).copy(bufferless = true)
case BroadcastKey => up(BroadcastKey, site).copy(bufferless = true)
})
/**
@ -159,7 +151,7 @@ class WithBufferlessBroadcastHub extends Config((site, here, up) => {
* DO NOT use this configuration.
*/
class WithStatelessBridge extends Config((site, here, up) => {
case BankedL2Params => up(BankedL2Params, site).copy(coherenceManager = { case (q, _) =>
case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = { case (q, _) =>
implicit val p = q
val cork = LazyModule(new TLCacheCork(unsafe = true))
(cork.node, cork.node)
@ -253,7 +245,7 @@ class WithRationalRocketTiles extends Config((site, here, up) => {
})
class WithEdgeDataBits(dataBits: Int) extends Config((site, here, up) => {
case MemoryBusParams => up(MemoryBusParams, site).copy(beatBytes = dataBits/8)
case MemoryBusKey => up(MemoryBusKey, site).copy(beatBytes = dataBits/8)
case ExtIn => up(ExtIn, site).copy(beatBytes = dataBits/8)
})
@ -263,11 +255,11 @@ class WithJtagDTM extends Config ((site, here, up) => {
})
class WithNoPeripheryArithAMO extends Config ((site, here, up) => {
case PeripheryBusParams => up(PeripheryBusParams, site).copy(arithmetic = false)
case PeripheryBusKey => up(PeripheryBusKey, site).copy(arithmetic = false)
})
class WithNBitPeripheryBus(nBits: Int) extends Config ((site, here, up) => {
case PeripheryBusParams => up(PeripheryBusParams, site).copy(beatBytes = nBits/8)
case PeripheryBusKey => up(PeripheryBusKey, site).copy(beatBytes = nBits/8)
})
class WithoutTLMonitors extends Config ((site, here, up) => {
@ -279,7 +271,7 @@ class WithNExtTopInterrupts(nExtInts: Int) extends Config((site, here, up) => {
})
class WithNMemoryChannels(n: Int) extends Config((site, here, up) => {
case BankedL2Params => up(BankedL2Params, site).copy(nMemoryChannels = n)
case BankedL2Key => up(BankedL2Key, site).copy(nMemoryChannels = n)
})
class WithExtMemSize(n: Long) extends Config((site, here, up) => {

4
src/main/scala/coreplex/FrontBus.scala
View File

@ -15,7 +15,7 @@ case class FrontBusParams(
slaveBuffering: BufferParams = BufferParams.default
) extends TLBusParams
case object FrontBusParams extends Field[FrontBusParams]
case object FrontBusKey extends Field[FrontBusParams]
class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "FrontBus") {
@ -50,7 +50,7 @@ class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrap
* for use in traits that connect individual devices or external ports.
*/
trait HasFrontBus extends HasSystemBus {
private val frontbusParams = p(FrontBusParams)
private val frontbusParams = p(FrontBusKey)
val frontbusBeatBytes = frontbusParams.beatBytes
val fbus = new FrontBus(frontbusParams)

2
src/main/scala/coreplex/InterruptBus.scala
View File

@ -30,7 +30,7 @@ trait HasInterruptBus {
}
/** Specifies the number of external interrupts */
case object NExtTopInterrupts extends Field[Int]
case object NExtTopInterrupts extends Field[Int](0)
/** This trait adds externally driven interrupts to the system.
* However, it should not be used directly; instead one of the below

18
src/main/scala/coreplex/MemoryBus.scala
View File

@ -9,13 +9,14 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
// TODO: applies to all caches, for now
case object CacheBlockBytes extends Field[Int]
case object CacheBlockBytes extends Field[Int](64)
/** L2 Broadcast Hub configuration */
case class BroadcastParams(
nTrackers: Int = 4,
bufferless: Boolean = false)
case object BroadcastParams extends Field[BroadcastParams]
case object BroadcastKey extends Field(BroadcastParams())
/** L2 memory subsystem configuration */
case class BankedL2Params(
@ -23,14 +24,15 @@ case class BankedL2Params(
nBanksPerChannel: Int = 1,
coherenceManager: (Parameters, HasMemoryBus) => (TLInwardNode, TLOutwardNode) = { case (q, _) =>
implicit val p = q
val MemoryBusParams(_, blockBytes, _, _) = p(MemoryBusParams)
val BroadcastParams(nTrackers, bufferless) = p(BroadcastParams)
val MemoryBusParams(_, blockBytes, _, _) = p(MemoryBusKey)
val BroadcastParams(nTrackers, bufferless) = p(BroadcastKey)
val bh = LazyModule(new TLBroadcast(blockBytes, nTrackers, bufferless))
(bh.node, bh.node)
}) {
val nBanks = nMemoryChannels*nBanksPerChannel
}
case object BankedL2Params extends Field[BankedL2Params]
case object BankedL2Key extends Field(BankedL2Params())
/** Parameterization of the memory-side bus created for each memory channel */
case class MemoryBusParams(
@ -40,7 +42,7 @@ case class MemoryBusParams(
slaveBuffering: BufferParams = BufferParams.none
) extends TLBusParams
case object MemoryBusParams extends Field[MemoryBusParams]
case object MemoryBusKey extends Field[MemoryBusParams]
/** Wrapper for creating TL nodes from a bus connected to the back of each mem channel */
class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "MemoryBus")(p) {
@ -50,9 +52,9 @@ class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWr
}
trait HasMemoryBus extends HasSystemBus with HasPeripheryBus with HasInterruptBus {
private val mbusParams = p(MemoryBusParams)
private val mbusParams = p(MemoryBusKey)
private val MemoryBusParams(beatBytes, blockBytes, _, _) = mbusParams
private val l2Params = p(BankedL2Params)
private val l2Params = p(BankedL2Key)
val BankedL2Params(nMemoryChannels, nBanksPerChannel, coherenceManager) = l2Params
val nBanks = l2Params.nBanks
val cacheBlockBytes = blockBytes

4
src/main/scala/coreplex/PeripheryBus.scala
View File

@ -19,7 +19,7 @@ case class PeripheryBusParams(
) extends TLBusParams {
}
case object PeripheryBusParams extends Field[PeripheryBusParams]
case object PeripheryBusKey extends Field[PeripheryBusParams]
class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "PeripheryBus") {
@ -42,7 +42,7 @@ class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends T
* for use in traits that connect individual devices or external ports.
*/
trait HasPeripheryBus extends HasSystemBus {
private val pbusParams = p(PeripheryBusParams)
private val pbusParams = p(PeripheryBusKey)
val pbusBeatBytes = pbusParams.beatBytes
val pbus = new PeripheryBus(pbusParams)

2
src/main/scala/coreplex/RTC.scala
View File

@ -8,7 +8,7 @@ import freechips.rocketchip.devices.tilelink.HasPeripheryClint
trait HasRTCModuleImp extends LazyMultiIOModuleImp {
val outer: HasPeripheryClint
private val pbusFreq = outer.p(PeripheryBusParams).frequency
private val pbusFreq = outer.p(PeripheryBusKey).frequency
private val rtcFreq = outer.p(DTSTimebase)
private val internalPeriod: BigInt = pbusFreq / rtcFreq

4
src/main/scala/coreplex/RocketCoreplex.scala
View File

@ -11,8 +11,8 @@ import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
case object RocketTilesKey extends Field[Seq[RocketTileParams]]
case object RocketCrossing extends Field[CoreplexClockCrossing]
case object RocketTilesKey extends Field[Seq[RocketTileParams]](Nil)
case object RocketCrossing extends Field[CoreplexClockCrossing](SynchronousCrossing())
trait HasRocketTiles extends HasSystemBus
with HasPeripheryBus

4
src/main/scala/coreplex/SystemBus.scala
View File

@ -15,7 +15,7 @@ case class SystemBusParams(
slaveBuffering: BufferParams = BufferParams.default
) extends TLBusParams
case object SystemBusParams extends Field[SystemBusParams]
case object SystemBusKey extends Field[SystemBusParams]
class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "SystemBus") {
@ -119,7 +119,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
* for use in traits that connect individual devices or external ports.
*/
trait HasSystemBus extends HasInterruptBus {
private val sbusParams = p(SystemBusParams)
private val sbusParams = p(SystemBusKey)
val sbusBeatBytes = sbusParams.beatBytes
val sbus = new SystemBus(sbusParams)