From b86f4b9bb7021511eec4248148037ecbf4972bac Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Fri, 8 Sep 2017 18:33:44 -0700 Subject: [PATCH] config: use Field defaults over Config defaults Also rename some keys that had the same class name as their value's class name. --- src/main/scala/config/Config.scala | 2 +- src/main/scala/coreplex/Configs.scala | 48 ++++++++----------- src/main/scala/coreplex/FrontBus.scala | 4 +- src/main/scala/coreplex/InterruptBus.scala | 2 +- src/main/scala/coreplex/MemoryBus.scala | 18 +++---- src/main/scala/coreplex/PeripheryBus.scala | 4 +- src/main/scala/coreplex/RTC.scala | 2 +- src/main/scala/coreplex/RocketCoreplex.scala | 4 +- src/main/scala/coreplex/SystemBus.scala | 4 +- .../scala/devices/debug/DebugTransport.scala | 2 +- src/main/scala/devices/debug/Periphery.scala | 2 +- src/main/scala/devices/tilelink/Clint.scala | 4 +- src/main/scala/devices/tilelink/Plic.scala | 4 +- src/main/scala/diplomacy/DeviceTree.scala | 2 +- src/main/scala/groundtest/Configs.scala | 4 +- src/main/scala/rocket/TLB.scala | 4 +- src/main/scala/system/Configs.scala | 13 ++--- src/main/scala/tilelink/Bus.scala | 2 +- 18 files changed, 57 insertions(+), 68 deletions(-) diff --git a/src/main/scala/config/Config.scala b/src/main/scala/config/Config.scala index 0f4db18e..45fec790 100644 --- a/src/main/scala/config/Config.scala +++ b/src/main/scala/config/Config.scala @@ -5,7 +5,7 @@ package freechips.rocketchip.config abstract class Field[T] private (val default: Option[T]) { def this() = this(None) - def this(x: T) = this(Some(x)) + def this(default: T) = this(Some(default)) } abstract class View { diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala index 2a074d1d..969982f2 100644 --- a/src/main/scala/coreplex/Configs.scala +++ b/src/main/scala/coreplex/Configs.scala @@ -16,25 +16,17 @@ import freechips.rocketchip.util._ class BaseCoreplexConfig extends Config ((site, here, up) => { // Tile parameters case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */ - case ASIdBits => 0 case XLen => 64 // Applies to all cores case MaxHartIdBits => log2Up(site(RocketTilesKey).size) case BuildCore => (p: Parameters) => new Rocket()(p) - case RocketTilesKey => Nil // Will be added by partial configs found below // Interconnect parameters - case RocketCrossing => SynchronousCrossing() - case BroadcastParams => BroadcastParams() - case BankedL2Params => BankedL2Params() - case SystemBusParams => SystemBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes)) - case PeripheryBusParams => PeripheryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes)) - case MemoryBusParams => MemoryBusParams(beatBytes = 8, blockBytes = site(CacheBlockBytes)) - case CacheBlockBytes => 64 - // Device parameters + case SystemBusKey => SystemBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes)) + case PeripheryBusKey => PeripheryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes)) + case MemoryBusKey => MemoryBusParams(beatBytes = 8, blockBytes = site(CacheBlockBytes)) + // Additional device Parameters + case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff))) + case BootROMParams => BootROMParams(contentFileName = "./bootrom/bootrom.img") case DebugModuleParams => DefaultDebugModuleParams(site(XLen)) - case PLICParams => PLICParams() - case ClintParams => ClintParams() - case DTSTimebase => BigInt(1000000) // 1 MHz - case TLBusDelayProbability => 0.0 }) /* Composable partial function Configs to set individual parameters */ @@ -47,11 +39,11 @@ class WithNBigCores(n: Int) extends Config((site, here, up) => { mulEarlyOut = true, divEarlyOut = true))), dcache = Some(DCacheParams( - rowBits = site(SystemBusParams).beatBits, + rowBits = site(SystemBusKey).beatBits, nMSHRs = 0, blockBytes = site(CacheBlockBytes))), icache = Some(ICacheParams( - rowBits = site(SystemBusParams).beatBits, + rowBits = site(SystemBusKey).beatBits, blockBytes = site(CacheBlockBytes)))) List.fill(n)(big) ++ up(RocketTilesKey, site) } @@ -63,14 +55,14 @@ class WithNSmallCores(n: Int) extends Config((site, here, up) => { core = RocketCoreParams(useVM = false, fpu = None), btb = None, dcache = Some(DCacheParams( - rowBits = site(SystemBusParams).beatBits, + rowBits = site(SystemBusKey).beatBits, nSets = 64, nWays = 1, nTLBEntries = 4, nMSHRs = 0, blockBytes = site(CacheBlockBytes))), icache = Some(ICacheParams( - rowBits = site(SystemBusParams).beatBits, + rowBits = site(SystemBusKey).beatBits, nSets = 64, nWays = 1, nTLBEntries = 4, @@ -89,7 +81,7 @@ class WithNTinyCores(n: Int) extends Config((site, here, up) => { mulDiv = Some(MulDivParams(mulUnroll = 8))), btb = None, dcache = Some(DCacheParams( - rowBits = site(SystemBusParams).beatBits, + rowBits = site(SystemBusKey).beatBits, nSets = 256, // 16Kb scratchpad nWays = 1, nTLBEntries = 4, @@ -97,7 +89,7 @@ class WithNTinyCores(n: Int) extends Config((site, here, up) => { blockBytes = site(CacheBlockBytes), scratch = Some(0x80000000L))), icache = Some(ICacheParams( - rowBits = site(SystemBusParams).beatBits, + rowBits = site(SystemBusKey).beatBits, nSets = 64, nWays = 1, nTLBEntries = 4, @@ -107,11 +99,11 @@ class WithNTinyCores(n: Int) extends Config((site, here, up) => { }) class WithNBanksPerMemChannel(n: Int) extends Config((site, here, up) => { - case BankedL2Params => up(BankedL2Params, site).copy(nBanksPerChannel = n) + case BankedL2Key => up(BankedL2Key, site).copy(nBanksPerChannel = n) }) class WithNTrackersPerBank(n: Int) extends Config((site, here, up) => { - case BroadcastParams => up(BroadcastParams, site).copy(nTrackers = n) + case BroadcastKey => up(BroadcastKey, site).copy(nTrackers = n) }) // This is the number of icache sets for all Rocket tiles @@ -143,7 +135,7 @@ class WithCacheBlockBytes(linesize: Int) extends Config((site, here, up) => { }) class WithBufferlessBroadcastHub extends Config((site, here, up) => { - case BroadcastParams => up(BroadcastParams, site).copy(bufferless = true) + case BroadcastKey => up(BroadcastKey, site).copy(bufferless = true) }) /** @@ -159,7 +151,7 @@ class WithBufferlessBroadcastHub extends Config((site, here, up) => { * DO NOT use this configuration. */ class WithStatelessBridge extends Config((site, here, up) => { - case BankedL2Params => up(BankedL2Params, site).copy(coherenceManager = { case (q, _) => + case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = { case (q, _) => implicit val p = q val cork = LazyModule(new TLCacheCork(unsafe = true)) (cork.node, cork.node) @@ -253,7 +245,7 @@ class WithRationalRocketTiles extends Config((site, here, up) => { }) class WithEdgeDataBits(dataBits: Int) extends Config((site, here, up) => { - case MemoryBusParams => up(MemoryBusParams, site).copy(beatBytes = dataBits/8) + case MemoryBusKey => up(MemoryBusKey, site).copy(beatBytes = dataBits/8) case ExtIn => up(ExtIn, site).copy(beatBytes = dataBits/8) }) @@ -263,11 +255,11 @@ class WithJtagDTM extends Config ((site, here, up) => { }) class WithNoPeripheryArithAMO extends Config ((site, here, up) => { - case PeripheryBusParams => up(PeripheryBusParams, site).copy(arithmetic = false) + case PeripheryBusKey => up(PeripheryBusKey, site).copy(arithmetic = false) }) class WithNBitPeripheryBus(nBits: Int) extends Config ((site, here, up) => { - case PeripheryBusParams => up(PeripheryBusParams, site).copy(beatBytes = nBits/8) + case PeripheryBusKey => up(PeripheryBusKey, site).copy(beatBytes = nBits/8) }) class WithoutTLMonitors extends Config ((site, here, up) => { @@ -279,7 +271,7 @@ class WithNExtTopInterrupts(nExtInts: Int) extends Config((site, here, up) => { }) class WithNMemoryChannels(n: Int) extends Config((site, here, up) => { - case BankedL2Params => up(BankedL2Params, site).copy(nMemoryChannels = n) + case BankedL2Key => up(BankedL2Key, site).copy(nMemoryChannels = n) }) class WithExtMemSize(n: Long) extends Config((site, here, up) => { diff --git a/src/main/scala/coreplex/FrontBus.scala b/src/main/scala/coreplex/FrontBus.scala index e51732a0..60be007e 100644 --- a/src/main/scala/coreplex/FrontBus.scala +++ b/src/main/scala/coreplex/FrontBus.scala @@ -15,7 +15,7 @@ case class FrontBusParams( slaveBuffering: BufferParams = BufferParams.default ) extends TLBusParams -case object FrontBusParams extends Field[FrontBusParams] +case object FrontBusKey extends Field[FrontBusParams] class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "FrontBus") { @@ -50,7 +50,7 @@ class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrap * for use in traits that connect individual devices or external ports. */ trait HasFrontBus extends HasSystemBus { - private val frontbusParams = p(FrontBusParams) + private val frontbusParams = p(FrontBusKey) val frontbusBeatBytes = frontbusParams.beatBytes val fbus = new FrontBus(frontbusParams) diff --git a/src/main/scala/coreplex/InterruptBus.scala b/src/main/scala/coreplex/InterruptBus.scala index d99b1734..3499a751 100644 --- a/src/main/scala/coreplex/InterruptBus.scala +++ b/src/main/scala/coreplex/InterruptBus.scala @@ -30,7 +30,7 @@ trait HasInterruptBus { } /** Specifies the number of external interrupts */ -case object NExtTopInterrupts extends Field[Int] +case object NExtTopInterrupts extends Field[Int](0) /** This trait adds externally driven interrupts to the system. * However, it should not be used directly; instead one of the below diff --git a/src/main/scala/coreplex/MemoryBus.scala b/src/main/scala/coreplex/MemoryBus.scala index 336bc529..4127426a 100644 --- a/src/main/scala/coreplex/MemoryBus.scala +++ b/src/main/scala/coreplex/MemoryBus.scala @@ -9,13 +9,14 @@ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ // TODO: applies to all caches, for now -case object CacheBlockBytes extends Field[Int] +case object CacheBlockBytes extends Field[Int](64) /** L2 Broadcast Hub configuration */ case class BroadcastParams( nTrackers: Int = 4, bufferless: Boolean = false) -case object BroadcastParams extends Field[BroadcastParams] + +case object BroadcastKey extends Field(BroadcastParams()) /** L2 memory subsystem configuration */ case class BankedL2Params( @@ -23,14 +24,15 @@ case class BankedL2Params( nBanksPerChannel: Int = 1, coherenceManager: (Parameters, HasMemoryBus) => (TLInwardNode, TLOutwardNode) = { case (q, _) => implicit val p = q - val MemoryBusParams(_, blockBytes, _, _) = p(MemoryBusParams) - val BroadcastParams(nTrackers, bufferless) = p(BroadcastParams) + val MemoryBusParams(_, blockBytes, _, _) = p(MemoryBusKey) + val BroadcastParams(nTrackers, bufferless) = p(BroadcastKey) val bh = LazyModule(new TLBroadcast(blockBytes, nTrackers, bufferless)) (bh.node, bh.node) }) { val nBanks = nMemoryChannels*nBanksPerChannel } -case object BankedL2Params extends Field[BankedL2Params] + +case object BankedL2Key extends Field(BankedL2Params()) /** Parameterization of the memory-side bus created for each memory channel */ case class MemoryBusParams( @@ -40,7 +42,7 @@ case class MemoryBusParams( slaveBuffering: BufferParams = BufferParams.none ) extends TLBusParams -case object MemoryBusParams extends Field[MemoryBusParams] +case object MemoryBusKey extends Field[MemoryBusParams] /** Wrapper for creating TL nodes from a bus connected to the back of each mem channel */ class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "MemoryBus")(p) { @@ -50,9 +52,9 @@ class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWr } trait HasMemoryBus extends HasSystemBus with HasPeripheryBus with HasInterruptBus { - private val mbusParams = p(MemoryBusParams) + private val mbusParams = p(MemoryBusKey) private val MemoryBusParams(beatBytes, blockBytes, _, _) = mbusParams - private val l2Params = p(BankedL2Params) + private val l2Params = p(BankedL2Key) val BankedL2Params(nMemoryChannels, nBanksPerChannel, coherenceManager) = l2Params val nBanks = l2Params.nBanks val cacheBlockBytes = blockBytes diff --git a/src/main/scala/coreplex/PeripheryBus.scala b/src/main/scala/coreplex/PeripheryBus.scala index 04ec0338..1de255ed 100644 --- a/src/main/scala/coreplex/PeripheryBus.scala +++ b/src/main/scala/coreplex/PeripheryBus.scala @@ -19,7 +19,7 @@ case class PeripheryBusParams( ) extends TLBusParams { } -case object PeripheryBusParams extends Field[PeripheryBusParams] +case object PeripheryBusKey extends Field[PeripheryBusParams] class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "PeripheryBus") { @@ -42,7 +42,7 @@ class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends T * for use in traits that connect individual devices or external ports. */ trait HasPeripheryBus extends HasSystemBus { - private val pbusParams = p(PeripheryBusParams) + private val pbusParams = p(PeripheryBusKey) val pbusBeatBytes = pbusParams.beatBytes val pbus = new PeripheryBus(pbusParams) diff --git a/src/main/scala/coreplex/RTC.scala b/src/main/scala/coreplex/RTC.scala index 60342481..b7fdba34 100644 --- a/src/main/scala/coreplex/RTC.scala +++ b/src/main/scala/coreplex/RTC.scala @@ -8,7 +8,7 @@ import freechips.rocketchip.devices.tilelink.HasPeripheryClint trait HasRTCModuleImp extends LazyMultiIOModuleImp { val outer: HasPeripheryClint - private val pbusFreq = outer.p(PeripheryBusParams).frequency + private val pbusFreq = outer.p(PeripheryBusKey).frequency private val rtcFreq = outer.p(DTSTimebase) private val internalPeriod: BigInt = pbusFreq / rtcFreq diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala index 087be550..f39f5db0 100644 --- a/src/main/scala/coreplex/RocketCoreplex.scala +++ b/src/main/scala/coreplex/RocketCoreplex.scala @@ -11,8 +11,8 @@ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ -case object RocketTilesKey extends Field[Seq[RocketTileParams]] -case object RocketCrossing extends Field[CoreplexClockCrossing] +case object RocketTilesKey extends Field[Seq[RocketTileParams]](Nil) +case object RocketCrossing extends Field[CoreplexClockCrossing](SynchronousCrossing()) trait HasRocketTiles extends HasSystemBus with HasPeripheryBus diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala index 4377da69..8e69c289 100644 --- a/src/main/scala/coreplex/SystemBus.scala +++ b/src/main/scala/coreplex/SystemBus.scala @@ -15,7 +15,7 @@ case class SystemBusParams( slaveBuffering: BufferParams = BufferParams.default ) extends TLBusParams -case object SystemBusParams extends Field[SystemBusParams] +case object SystemBusKey extends Field[SystemBusParams] class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "SystemBus") { @@ -119,7 +119,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr * for use in traits that connect individual devices or external ports. */ trait HasSystemBus extends HasInterruptBus { - private val sbusParams = p(SystemBusParams) + private val sbusParams = p(SystemBusKey) val sbusBeatBytes = sbusParams.beatBytes val sbus = new SystemBus(sbusParams) diff --git a/src/main/scala/devices/debug/DebugTransport.scala b/src/main/scala/devices/debug/DebugTransport.scala index 44b535e9..7a5dd8d2 100644 --- a/src/main/scala/devices/debug/DebugTransport.scala +++ b/src/main/scala/devices/debug/DebugTransport.scala @@ -19,7 +19,7 @@ case class JtagDTMConfig ( // the lines of p(JtagDTMKey).idcodeManufId.U(11.W). debugIdleCycles : Int) -case object JtagDTMKey extends Field[JtagDTMConfig] +case object JtagDTMKey extends Field[JtagDTMConfig](new JtagDTMKeyDefault()) class JtagDTMKeyDefault extends JtagDTMConfig( idcodeVersion = 0, diff --git a/src/main/scala/devices/debug/Periphery.scala b/src/main/scala/devices/debug/Periphery.scala index 776c0632..9ab84e8b 100644 --- a/src/main/scala/devices/debug/Periphery.scala +++ b/src/main/scala/devices/debug/Periphery.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.jtag._ import freechips.rocketchip.util._ /** A knob selecting one of the two possible debug interfaces */ -case object IncludeJtagDTM extends Field[Boolean] +case object IncludeJtagDTM extends Field[Boolean](false) /** A wrapper bundle containing one of the two possible debug interfaces */ class DebugIO(implicit p: Parameters) extends ParameterizedBundle()(p) { diff --git a/src/main/scala/devices/tilelink/Clint.scala b/src/main/scala/devices/tilelink/Clint.scala index 2848ed4c..13627529 100644 --- a/src/main/scala/devices/tilelink/Clint.scala +++ b/src/main/scala/devices/tilelink/Clint.scala @@ -30,7 +30,7 @@ case class ClintParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0) def address = AddressSet(baseAddress, ClintConsts.size-1) } -case object ClintParams extends Field[ClintParams] +case object ClintKey extends Field(ClintParams()) class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) extends LazyModule { @@ -96,6 +96,6 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte /** Trait that will connect a Clint to a coreplex */ trait HasPeripheryClint extends HasPeripheryBus { - val clint = LazyModule(new CoreplexLocalInterrupter(p(ClintParams))) + val clint = LazyModule(new CoreplexLocalInterrupter(p(ClintKey))) clint.node := pbus.toVariableWidthSlaves } diff --git a/src/main/scala/devices/tilelink/Plic.scala b/src/main/scala/devices/tilelink/Plic.scala index 94b0e186..44268ca1 100644 --- a/src/main/scala/devices/tilelink/Plic.scala +++ b/src/main/scala/devices/tilelink/Plic.scala @@ -58,7 +58,7 @@ case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, i def address = AddressSet(baseAddress, PLICConsts.size-1) } -case object PLICParams extends Field[PLICParams] +case object PLICKey extends Field(PLICParams()) /** Platform-Level Interrupt Controller */ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule @@ -238,7 +238,7 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule /** Trait that will connect a PLIC to a coreplex */ trait HasPeripheryPLIC extends HasInterruptBus with HasPeripheryBus { - val plic = LazyModule(new TLPLIC(p(PLICParams))) + val plic = LazyModule(new TLPLIC(p(PLICKey))) plic.node := pbus.toVariableWidthSlaves plic.intnode := ibus.toPLIC } diff --git a/src/main/scala/diplomacy/DeviceTree.scala b/src/main/scala/diplomacy/DeviceTree.scala index b27bb02f..42ce987a 100644 --- a/src/main/scala/diplomacy/DeviceTree.scala +++ b/src/main/scala/diplomacy/DeviceTree.scala @@ -8,7 +8,7 @@ import java.io.{ByteArrayInputStream, ByteArrayOutputStream} case object DTSModel extends Field[String] case object DTSCompat extends Field[Seq[String]] // -dev, -soc -case object DTSTimebase extends Field[BigInt] // Clock frequency of clint RTC (use 0 if you don't know it) +case object DTSTimebase extends Field[BigInt](0) // Clock frequency of clint RTC (use 0 if you don't know it) object DTS { diff --git a/src/main/scala/groundtest/Configs.scala b/src/main/scala/groundtest/Configs.scala index d40ec8ea..067202a8 100644 --- a/src/main/scala/groundtest/Configs.scala +++ b/src/main/scala/groundtest/Configs.scala @@ -25,8 +25,8 @@ class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) extends Config( addrBag = { val nSets = 2 val nWays = 1 - val blockOffset = site(SystemBusParams).blockOffset - val nBeats = site(SystemBusParams).blockBeats + val blockOffset = site(SystemBusKey).blockOffset + val nBeats = site(SystemBusKey).blockBeats List.tabulate(4 * nWays) { i => Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) } }.flatten diff --git a/src/main/scala/rocket/TLB.scala b/src/main/scala/rocket/TLB.scala index 4d51f619..da25dd0e 100644 --- a/src/main/scala/rocket/TLB.scala +++ b/src/main/scala/rocket/TLB.scala @@ -13,8 +13,8 @@ import freechips.rocketchip.tile.{XLen, CoreModule, CoreBundle} import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ -case object PgLevels extends Field[Int] -case object ASIdBits extends Field[Int] +case object PgLevels extends Field[Int](2) +case object ASIdBits extends Field[Int](0) class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) { val rs1 = Bool() diff --git a/src/main/scala/system/Configs.scala b/src/main/scala/system/Configs.scala index 884702f4..187e127f 100644 --- a/src/main/scala/system/Configs.scala +++ b/src/main/scala/system/Configs.scala @@ -6,32 +6,27 @@ package freechips.rocketchip.system import Chisel._ import freechips.rocketchip.config.Config import freechips.rocketchip.coreplex._ -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.devices.debug.{IncludeJtagDTM, JtagDTMKey} import freechips.rocketchip.diplomacy._ class BaseConfig extends Config(new BaseCoreplexConfig().alter((site,here,up) => { // DTS descriptive parameters case DTSModel => "freechips,rocketchip-unknown" case DTSCompat => Nil + case DTSTimebase => BigInt(1000000) // 1 MHz // External port parameters - case IncludeJtagDTM => false - case JtagDTMKey => new JtagDTMKeyDefault() case NExtTopInterrupts => 2 case ExtMem => MasterPortParams( base = x"8000_0000", size = x"1000_0000", - beatBytes = site(MemoryBusParams).beatBytes, + beatBytes = site(MemoryBusKey).beatBytes, idBits = 4) case ExtBus => MasterPortParams( base = x"6000_0000", size = x"2000_0000", - beatBytes = site(MemoryBusParams).beatBytes, + beatBytes = site(MemoryBusKey).beatBytes, idBits = 4) case ExtIn => SlavePortParams(beatBytes = 8, idBits = 8, sourceBits = 4) - // Additional device Parameters - case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff))) - case BootROMParams => BootROMParams(contentFileName = "./bootrom/bootrom.img") })) class DefaultConfig extends Config(new WithNBigCores(1) ++ new BaseConfig) diff --git a/src/main/scala/tilelink/Bus.scala b/src/main/scala/tilelink/Bus.scala index 0dcb5b7a..b08fa109 100644 --- a/src/main/scala/tilelink/Bus.scala +++ b/src/main/scala/tilelink/Bus.scala @@ -6,7 +6,7 @@ import Chisel._ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ -case object TLBusDelayProbability extends Field[Double] +case object TLBusDelayProbability extends Field[Double](0.0) /** Specifies widths of various attachement points in the SoC */ trait TLBusParams {