riscv/rocket-chip
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Update to new ISA

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This commit is contained in:
Andrew Waterman 2013-09-21 06:40:23 -07:00
parent 09247c0e0b
commit b7d7ced41b
4 changed files with 6 additions and 6 deletions
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2
emulator/Makefile
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@ -82,7 +82,7 @@ output/%.out: output/%.hex emulator
output/%.vpd: output/%.hex emulator-debug output/%.vpd: output/%.hex emulator-debug
rm -rf $@.vcd && mkfifo $@.vcd rm -rf $@.vcd && mkfifo $@.vcd
vcd2vpd $@.vcd $@ > /dev/null & vcd2vpd $@.vcd $@ > /dev/null &
./emulator-debug +dramsim +max-cycles=30000000 +verbose -v$@.vcd +coremap-random +loadmem=$< none 2> $(patsubst %.vpd,%.out,$@) ./emulator-debug +dramsim +max-cycles=30000000 +verbose -v$@.vcd +coremap-random +loadmem=$< none $(disasm) $(patsubst %.vpd,%.out,$@)
run-asm-tests: $(addprefix output/, $(addsuffix .out, $(asm_p_tests) $(asm_v_tests))) run-asm-tests: $(addprefix output/, $(addsuffix .out, $(asm_p_tests) $(asm_v_tests)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo; @echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo;

2
riscv-tests

@ -1 +1 @@
Subproject commit 324c290f32f9c6e8953f14529d1e86659b2a2239 Subproject commit 8dd97c2e7af399bc04b9d132bd1f1a4bdbbfec57

2
rocket

@ -1 +1 @@
Subproject commit 92a7abd47a9a73b6fde280bedc71d23fd7d0eede Subproject commit 06b1b7cddeab60acaf8c5c8393cfbe9941549618

6
src/main/scala/RocketChip.scala
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@ -14,7 +14,7 @@ object DummyTopLevelConstants {
val HTIF_WIDTH = 16 val HTIF_WIDTH = 16
val ENABLE_SHARING = true val ENABLE_SHARING = true
val ENABLE_CLEAN_EXCLUSIVE = true val ENABLE_CLEAN_EXCLUSIVE = true
val HAS_FPU = false val HAS_FPU = true
val NL2_REL_XACTS = 1 val NL2_REL_XACTS = 1
val NL2_ACQ_XACTS = 7 val NL2_ACQ_XACTS = 7
val NMSHRS = 2 val NMSHRS = 2
@ -97,8 +97,8 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
val llc_tag_leaf = Mem(Bits(width = 152), 512, seqRead = true) val llc_tag_leaf = Mem(Bits(width = 152), 512, seqRead = true)
val llc_data_leaf = Mem(Bits(width = 64), 4096, seqRead = true) val llc_data_leaf = Mem(Bits(width = 64), 4096, seqRead = true)
//val llc = Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16, tagLeaf=llc_tag_leaf, dataLeaf=llc_data_leaf)) val llc = Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16, tagLeaf=llc_tag_leaf, dataLeaf=llc_data_leaf))
val llc = Module(new DRAMSideLLCNull(NL2_REL_XACTS+NL2_ACQ_XACTS, REFILL_CYCLES)) //val llc = Module(new DRAMSideLLCNull(NL2_REL_XACTS+NL2_ACQ_XACTS, REFILL_CYCLES))
val mem_serdes = Module(new MemSerdes(htif_width)) val mem_serdes = Module(new MemSerdes(htif_width))
require(clientEndpoints.length == ln.nClients) require(clientEndpoints.length == ln.nClients)