diff --git a/emulator/Makefile b/emulator/Makefile
index 028a44e3..c309313d 100644
--- a/emulator/Makefile
+++ b/emulator/Makefile
@@ -82,7 +82,7 @@ output/%.out: output/%.hex emulator
 output/%.vpd: output/%.hex emulator-debug
 	rm -rf $@.vcd && mkfifo $@.vcd
 	vcd2vpd $@.vcd $@ > /dev/null &
-	./emulator-debug +dramsim +max-cycles=30000000 +verbose -v$@.vcd +coremap-random +loadmem=$< none 2> $(patsubst %.vpd,%.out,$@)
+	./emulator-debug +dramsim +max-cycles=30000000 +verbose -v$@.vcd +coremap-random +loadmem=$< none $(disasm) $(patsubst %.vpd,%.out,$@)
 
 run-asm-tests: $(addprefix output/, $(addsuffix .out, $(asm_p_tests) $(asm_v_tests)))
 	@echo; perl -ne 'print "  [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo;
diff --git a/riscv-tests b/riscv-tests
index 324c290f..8dd97c2e 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit 324c290f32f9c6e8953f14529d1e86659b2a2239
+Subproject commit 8dd97c2e7af399bc04b9d132bd1f1a4bdbbfec57
diff --git a/rocket b/rocket
index 92a7abd4..06b1b7cd 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit 92a7abd47a9a73b6fde280bedc71d23fd7d0eede
+Subproject commit 06b1b7cddeab60acaf8c5c8393cfbe9941549618
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index ba778ccd..1577df10 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -14,7 +14,7 @@ object DummyTopLevelConstants {
   val HTIF_WIDTH = 16
   val ENABLE_SHARING = true
   val ENABLE_CLEAN_EXCLUSIVE = true
-  val HAS_FPU = false
+  val HAS_FPU = true
   val NL2_REL_XACTS = 1
   val NL2_ACQ_XACTS = 7
   val NMSHRS = 2
@@ -97,8 +97,8 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
 
   val llc_tag_leaf = Mem(Bits(width = 152), 512, seqRead = true)
   val llc_data_leaf = Mem(Bits(width = 64), 4096, seqRead = true)
-  //val llc = Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16, tagLeaf=llc_tag_leaf, dataLeaf=llc_data_leaf))
-  val llc = Module(new DRAMSideLLCNull(NL2_REL_XACTS+NL2_ACQ_XACTS, REFILL_CYCLES))
+  val llc = Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16, tagLeaf=llc_tag_leaf, dataLeaf=llc_data_leaf))
+  //val llc = Module(new DRAMSideLLCNull(NL2_REL_XACTS+NL2_ACQ_XACTS, REFILL_CYCLES))
   val mem_serdes = Module(new MemSerdes(htif_width))
 
   require(clientEndpoints.length == ln.nClients)