riscv/rocket-chip
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no vector interrupt masking

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This commit is contained in:
Yunsup Lee 2012-03-17 23:00:27 -07:00
parent 8a4f95e617
commit b793d63182
1 changed files with 2 additions and 3 deletions
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5
rocket/src/main/scala/ctrl.scala
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@ -648,17 +648,16 @@ class rocketCtrl extends Component
// FIXME: verify PC in MEM stage points to valid, restartable instruction // FIXME: verify PC in MEM stage points to valid, restartable instruction
val p_irq_timer = (io.dpath.status(15).toBool && io.dpath.irq_timer); val p_irq_timer = (io.dpath.status(15).toBool && io.dpath.irq_timer);
val p_irq_ipi = (io.dpath.status(13).toBool && io.dpath.irq_ipi); val p_irq_ipi = (io.dpath.status(13).toBool && io.dpath.irq_ipi);
val p_irq_vec = (io.dpath.status(8) && vec_irq)
val interrupt = val interrupt =
io.dpath.status(SR_ET).toBool && mem_reg_valid && io.dpath.status(SR_ET).toBool && mem_reg_valid &&
((io.dpath.status(15).toBool && io.dpath.irq_timer) || ((io.dpath.status(15).toBool && io.dpath.irq_timer) ||
(io.dpath.status(13).toBool && io.dpath.irq_ipi) || (io.dpath.status(13).toBool && io.dpath.irq_ipi) ||
p_irq_vec); vec_irq);
val interrupt_cause = val interrupt_cause =
Mux(p_irq_ipi, UFix(21,5), Mux(p_irq_ipi, UFix(21,5),
Mux(p_irq_timer, UFix(23,5), Mux(p_irq_timer, UFix(23,5),
Mux(p_irq_vec, vec_irq_cause, Mux(vec_irq, vec_irq_cause,
UFix(0,5)))) UFix(0,5))))
val mem_xcpt_ma_ld = io.dmem.xcpt_ma_ld && !mem_reg_kill val mem_xcpt_ma_ld = io.dmem.xcpt_ma_ld && !mem_reg_kill