From b793d63182f94e0dda34f8809e281d1d84c28c6b Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 17 Mar 2012 23:00:27 -0700 Subject: [PATCH] no vector interrupt masking --- rocket/src/main/scala/ctrl.scala | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index 801198ef..14b74cbc 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -648,17 +648,16 @@ class rocketCtrl extends Component // FIXME: verify PC in MEM stage points to valid, restartable instruction val p_irq_timer = (io.dpath.status(15).toBool && io.dpath.irq_timer); val p_irq_ipi = (io.dpath.status(13).toBool && io.dpath.irq_ipi); - val p_irq_vec = (io.dpath.status(8) && vec_irq) val interrupt = io.dpath.status(SR_ET).toBool && mem_reg_valid && ((io.dpath.status(15).toBool && io.dpath.irq_timer) || (io.dpath.status(13).toBool && io.dpath.irq_ipi) || - p_irq_vec); + vec_irq); val interrupt_cause = Mux(p_irq_ipi, UFix(21,5), Mux(p_irq_timer, UFix(23,5), - Mux(p_irq_vec, vec_irq_cause, + Mux(vec_irq, vec_irq_cause, UFix(0,5)))) val mem_xcpt_ma_ld = io.dmem.xcpt_ma_ld && !mem_reg_kill