riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Merge branch 'master' into test-harness-fixes

Browse Source
This commit is contained in:
Andrew Waterman 2016-08-19 22:53:12 -07:00 committed by GitHub
commit b7181ba49b
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/coreplex/Coreplex.scala
View File

@ -193,7 +193,9 @@ class DefaultOuterMemorySystem(implicit p: Parameters) extends OuterMemorySystem
case InnerTLId => "L1toL2"
case OuterTLId => "L2toMMIO"
})))
io.mmio <> mmioManager.io.outer
io.mmio.acquire <> Queue(mmioManager.io.outer.acquire, 1)
mmioManager.io.outer.grant <> Queue(io.mmio.grant, 1)
// Wire the tiles to the TileLink client ports of the L1toL2 network,
// and coherence manager(s) to the other side