riscv/rocket-chip
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nbdcache, writeback unit: when release is not ready and data is not ready for a beat too, no need to re-read data array.

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This commit is contained in:
Wei Song 2015-05-30 16:25:27 +01:00
parent 6a9390c50e
commit b6e68773fd
1 changed files with 7 additions and 5 deletions
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12
rocket/src/main/scala/nbdcache.scala
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@ -409,11 +409,13 @@ class WritebackUnit extends L1HellaCacheModule {
} }
when (r2_data_req_fired) { when (r2_data_req_fired) {
io.release.valid := beat_done io.release.valid := beat_done
when(!io.release.ready) { when(beat_done) {
r1_data_req_fired := false when(!io.release.ready) {
r2_data_req_fired := false r1_data_req_fired := false
data_req_cnt := data_req_cnt - Mux[UInt](Bool(refillCycles > 1) && r1_data_req_fired, 2, 1) r2_data_req_fired := false
} .elsewhen(beat_done) { if(refillCyclesPerBeat > 1) buf_v := 0 } data_req_cnt := data_req_cnt - Mux[UInt](Bool(refillCycles > 1) && r1_data_req_fired, 2, 1)
} .otherwise { if(refillCyclesPerBeat > 1) buf_v := 0 }
}
when(!r1_data_req_fired) { when(!r1_data_req_fired) {
// We're done if this is the final data request and the Release can be sent // We're done if this is the final data request and the Release can be sent
active := data_req_cnt < UInt(refillCycles) || !io.release.ready active := data_req_cnt < UInt(refillCycles) || !io.release.ready