riscv/rocket-chip
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tile: add option for tile boundary buffers

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This commit is contained in:
Henry Cook
2017-07-27 17:30:51 -07:00
parent 289ef30dbc
commit b64b87ad07
1 changed files with 12 additions and 7 deletions
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19
src/main/scala/tile/RocketTile.scala
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@@ -17,7 +17,8 @@ case class RocketTileParams(
dcache: Option[DCacheParams] = Some(DCacheParams()),
rocc: Seq[RoCCParams] = Nil,
btb: Option[BTBParams] = Some(BTBParams()),
dataScratchpadBytes: Int = 0) extends TileParams {
dataScratchpadBytes: Int = 0,
boundaryBufferParams: BufferParams = BufferParams.flow) extends TileParams {
require(icache.isDefined)
require(dcache.isDefined)
}
@@ -171,7 +172,11 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
val periphIntNode = IntInputNode()
val coreIntNode = IntInputNode()
val intXbar = LazyModule(new IntXbar)
val masterBuffer = LazyModule(new TLBuffer(rtp.boundaryBufferParams))
val slaveBuffer = LazyModule(new TLBuffer(rtp.boundaryBufferParams))
masterBuffer.node :=* rocket.masterNode
rocket.slaveNode connectButDontMonitorSlaves slaveBuffer.node
rocket.intNode := intXbar.intnode
lazy val module = new LazyModuleImp(this) {
@@ -190,10 +195,10 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
val masterNode = TLOutputNode()
masterNode :=* rocket.masterNode
masterNode :=* masterBuffer.node
val slaveNode = new TLInputNode() { override def reverse = true }
rocket.slaveNode connectButDontMonitorSlaves slaveNode
slaveBuffer.node connectButDontMonitorSlaves slaveNode
// Fully async interrupts need synchronizers.
// Others need no synchronization.
@@ -208,12 +213,12 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters)
class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
val masterNode = TLAsyncOutputNode()
val source = LazyModule(new TLAsyncCrossingSource)
source.node :=* rocket.masterNode
source.node :=* masterBuffer.node
masterNode :=* source.node
val slaveNode = new TLAsyncInputNode() { override def reverse = true }
val sink = LazyModule(new TLAsyncCrossingSink)
rocket.slaveNode connectButDontMonitorSlaves sink.node
slaveBuffer.node connectButDontMonitorSlaves sink.node
sink.node connectButDontMonitorSlaves slaveNode
// Fully async interrupts need synchronizers,
@@ -232,12 +237,12 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters
class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
val masterNode = TLRationalOutputNode()
val source = LazyModule(new TLRationalCrossingSource)
source.node :=* rocket.masterNode
source.node :=* masterBuffer.node
masterNode :=* source.node
val slaveNode = new TLRationalInputNode() { override def reverse = true }
val sink = LazyModule(new TLRationalCrossingSink(SlowToFast))
rocket.slaveNode connectButDontMonitorSlaves sink.node
slaveBuffer.node connectButDontMonitorSlaves sink.node
sink.node connectButDontMonitorSlaves slaveNode
// Fully async interrupts need synchronizers.