From b64b87ad0778582bb8583567d1d653f61f230a28 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Thu, 27 Jul 2017 17:30:51 -0700
Subject: [PATCH] tile: add option for tile boundary buffers

---
 src/main/scala/tile/RocketTile.scala | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
index 4bb6661e..7afcb64d 100644
--- a/src/main/scala/tile/RocketTile.scala
+++ b/src/main/scala/tile/RocketTile.scala
@@ -17,7 +17,8 @@ case class RocketTileParams(
     dcache: Option[DCacheParams] = Some(DCacheParams()),
     rocc: Seq[RoCCParams] = Nil,
     btb: Option[BTBParams] = Some(BTBParams()),
-    dataScratchpadBytes: Int = 0) extends TileParams {
+    dataScratchpadBytes: Int = 0,
+    boundaryBufferParams: BufferParams = BufferParams.flow) extends TileParams {
   require(icache.isDefined)
   require(dcache.isDefined)
 }
@@ -171,7 +172,11 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
   val periphIntNode  = IntInputNode()
   val coreIntNode    = IntInputNode()
   val intXbar = LazyModule(new IntXbar)
+  val masterBuffer = LazyModule(new TLBuffer(rtp.boundaryBufferParams))
+  val slaveBuffer = LazyModule(new TLBuffer(rtp.boundaryBufferParams))
 
+  masterBuffer.node :=* rocket.masterNode
+  rocket.slaveNode connectButDontMonitorSlaves slaveBuffer.node
   rocket.intNode := intXbar.intnode
 
   lazy val module = new LazyModuleImp(this) {
@@ -190,10 +195,10 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
 
 class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
   val masterNode = TLOutputNode()
-  masterNode :=* rocket.masterNode
+  masterNode :=* masterBuffer.node
 
   val slaveNode = new TLInputNode() { override def reverse = true }
-  rocket.slaveNode connectButDontMonitorSlaves slaveNode
+  slaveBuffer.node connectButDontMonitorSlaves slaveNode
 
   // Fully async interrupts need synchronizers.
   // Others need no synchronization.
@@ -208,12 +213,12 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters)
 class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
   val masterNode = TLAsyncOutputNode()
   val source = LazyModule(new TLAsyncCrossingSource)
-  source.node :=* rocket.masterNode
+  source.node :=* masterBuffer.node
   masterNode :=* source.node
 
   val slaveNode = new TLAsyncInputNode() { override def reverse = true }
   val sink = LazyModule(new TLAsyncCrossingSink)
-  rocket.slaveNode connectButDontMonitorSlaves sink.node
+  slaveBuffer.node connectButDontMonitorSlaves sink.node
   sink.node connectButDontMonitorSlaves slaveNode
 
   // Fully async interrupts need synchronizers,
@@ -232,12 +237,12 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters
 class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
   val masterNode = TLRationalOutputNode()
   val source = LazyModule(new TLRationalCrossingSource)
-  source.node :=* rocket.masterNode
+  source.node :=* masterBuffer.node
   masterNode :=* source.node
 
   val slaveNode = new TLRationalInputNode() { override def reverse = true }
   val sink = LazyModule(new TLRationalCrossingSink(SlowToFast))
-  rocket.slaveNode connectButDontMonitorSlaves sink.node
+  slaveBuffer.node connectButDontMonitorSlaves sink.node
   sink.node connectButDontMonitorSlaves slaveNode
 
   // Fully async interrupts need synchronizers.