riscv/rocket-chip
1
0 Fork 0
Code Releases Activity

system: fix DefaultFPGAConfig (#1047)

Browse Source 
It was missing cores. Fixes #736.
This commit is contained in:
Wesley W. Terpstra authored and GitHub committed 2017-10-11 10:48:41 -07:00
1 parent 8e1a002c4e
commit b566ffedea
1 file changed
+4 -2
Download Patch File Download Diff File Expand all files Collapse all files
src/main/scala/system/Configs.scala
+4 -2
View File
@@ -69,6 +69,8 @@ class TinyConfig extends Config(
new WithNTinyCores(1) ++
new BaseConfig)
class DefaultFPGAConfig extends Config(new BaseConfig)
class DefaultFPGASmallConfig extends Config(new WithNSmallCores(1) ++ new DefaultFPGAConfig)
class BaseFPGAConfig extends Config(new BaseConfig)
class DefaultFPGAConfig extends Config(new WithNSmallCores(1) ++ new BaseFPGAConfig)
class DefaultFPGASmallConfig extends Config(new DefaultFPGAConfig)