riscv/rocket-chip
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clean up I$ parity code

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This commit is contained in:
Andrew Waterman
2012-11-24 22:00:43 -08:00
parent 55082e45c4
commit b514c7b725
2 changed files with 54 additions and 38 deletions
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27
rocket/src/main/scala/icache.scala
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@ -7,7 +7,7 @@ import uncore._
import Util._
case class ICacheConfig(sets: Int, assoc: Int, co: CoherencePolicyWithUncached,
parity: Boolean = false)
code: Code = new IdentityCode)
{
val w = 1
val ibytes = 4
@ -15,12 +15,10 @@ case class ICacheConfig(sets: Int, assoc: Int, co: CoherencePolicyWithUncached,
val dm = assoc == 1
val lines = sets * assoc
val databits = MEM_DATA_BITS
val datawidth = databits + (if (parity) 1 else 0)
val idxbits = log2Up(sets)
val offbits = OFFSET_BITS
val untagbits = idxbits + offbits
val tagbits = PADDR_BITS - untagbits
val tagwidth = tagbits + (if (parity) 1 else 0)
require(isPow2(sets) && isPow2(assoc))
require(isPow2(w) && isPow2(ibytes))
@ -176,11 +174,12 @@ class ICache(implicit c: ICacheConfig) extends Component
val (rf_cnt, refill_done) = Counter(io.mem.xact_rep.valid, REFILL_CYCLES)
val repl_way = if (c.dm) UFix(0) else LFSR16(s2_miss)(log2Up(c.assoc)-1,0)
val tag_array = Mem(c.sets, seqRead = true) { Bits(width = c.tagwidth*c.assoc) }
val enc_tagbits = c.code.width(c.tagbits)
val tag_array = Mem(c.sets, seqRead = true) { Bits(width = enc_tagbits*c.assoc) }
val tag_rdata = Reg() { Bits() }
when (refill_done) {
val wmask = FillInterleaved(c.tagwidth, if (c.dm) Bits(1) else UFixToOH(repl_way))
val tag = Cat(if (c.parity) s2_tag.xorR else null, s2_tag)
val wmask = FillInterleaved(enc_tagbits, if (c.dm) Bits(1) else UFixToOH(repl_way))
val tag = c.code.encode(s2_tag)
tag_array.write(s2_idx, Fill(c.assoc, tag), wmask)
}
/*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM
@ -201,39 +200,37 @@ class ICache(implicit c: ICacheConfig) extends Component
val s1_tag_match = Vec(c.assoc) { Bool() }
val s2_tag_hit = Vec(c.assoc) { Bool() }
val s2_data_disparity = Vec(c.assoc) { Bool() }
val s2_dout = Vec(c.assoc){Reg{Bits()}}
for (i <- 0 until c.assoc) {
val s1_vb = vb_array(Cat(UFix(i), s1_pgoff(c.untagbits-1,c.offbits))).toBool
val s2_vb = Reg() { Bool() }
val s2_tag_disparity = Reg() { Bool() }
val s2_tag_match = Reg() { Bool() }
val tag_out = tag_rdata(c.tagwidth*(i+1)-1, c.tagwidth*i)
val tag_out = tag_rdata(enc_tagbits*(i+1)-1, enc_tagbits*i)
when (s1_valid && rdy && !stall) {
s2_vb := s1_vb
s2_tag_disparity := tag_out.xorR
s2_tag_disparity := c.code.decode(tag_out).error
s2_tag_match := s1_tag_match(i)
}
s1_tag_match(i) := tag_out(c.tagbits-1,0) === s1_tag
s2_tag_hit(i) := s2_vb && s2_tag_match
s2_disparity(i) := Bool(c.parity) && s2_vb && (s2_tag_disparity || s2_data_disparity(i))
s2_disparity(i) := s2_vb && (s2_tag_disparity || c.code.decode(s2_dout(i)).error)
}
s2_any_tag_hit := s2_tag_hit.reduceLeft(_||_) && !s2_disparity.reduceLeft(_||_)
val s2_dout = Vec(c.assoc) { Reg() { Bits(width = c.databits) } }
for (i <- 0 until c.assoc) {
val data_array = Mem(c.sets*REFILL_CYCLES, seqRead = true){ Bits(width = c.datawidth) }
val data_array = Mem(c.sets*REFILL_CYCLES, seqRead = true){ Bits(width = c.code.width(c.databits)) }
val s1_dout = Reg(){ Bits() }
when (io.mem.xact_rep.valid && repl_way === UFix(i)) {
val d = io.mem.xact_rep.bits.data
val wdata = if (c.parity) Cat(d.xorR, d) else d
data_array(Cat(s2_idx,rf_cnt)) := wdata
data_array(Cat(s2_idx,rf_cnt)) := c.code.encode(d)
}
/*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM
s1_dout := data_array(s0_pgoff(c.untagbits-1,c.offbits-rf_cnt.getWidth))
}
// if s1_tag_match is critical, replace with partial tag check
when (s1_valid && rdy && !stall && (Bool(c.dm) || s1_tag_match(i))) { s2_dout(i) := s1_dout }
s2_data_disparity(i) := s2_dout(i).xorR
}
val s2_dout_word = s2_dout.map(x => (x >> (s2_offset(log2Up(c.databits/8)-1,log2Up(c.ibytes)) << log2Up(c.ibytes*8)))(c.ibytes*8-1,0))
io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word)