coreplex: RocketTileWrapper now HasCrossingHelper
This commit is contained in:
committed by
Wesley W. Terpstra
parent
9fe35382ea
commit
b48ab985d0
@ -19,7 +19,6 @@ case class RocketTileParams(
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rocc: Seq[RoCCParams] = Nil,
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btb: Option[BTBParams] = Some(BTBParams()),
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dataScratchpadBytes: Int = 0,
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boundaryBuffers: Boolean = false,
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trace: Boolean = false,
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hcfOnUncorrectable: Boolean = false,
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name: Option[String] = Some("tile"),
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@ -188,38 +187,29 @@ class RocketTileWrapperBundle[+L <: RocketTileWrapper](_outer: L) extends BaseTi
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val halt_and_catch_fire = _outer.rocket.module.io.halt_and_catch_fire.map(_.cloneType)
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}
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abstract class RocketTileWrapper(rtp: RocketTileParams)(implicit p: Parameters) extends BaseTile(rtp) {
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val rocket = LazyModule(new RocketTile(rtp))
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val asyncIntNode : IntInwardNode
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val periphIntNode : IntInwardNode
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val coreIntNode : IntInwardNode
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val intOutputNode = rocket.intOutputNode
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class RocketTileWrapper(
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params: RocketTileParams,
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val crossing: CoreplexClockCrossing,
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val boundaryBuffers: Boolean = false)
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(implicit p: Parameters) extends BaseTile(params) with HasCrossingHelper {
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val rocket = LazyModule(new RocketTile(params))
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val masterBuffer = LazyModule(new TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)))
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val masterNode: TLOutwardNode = if (boundaryBuffers) {
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masterBuffer.node :=* rocket.masterNode
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masterBuffer.node
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} else { rocket.masterNode }
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val slaveBuffer = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none))
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val slaveNode: TLInwardNode = DisableMonitors { implicit p => if (boundaryBuffers) {
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rocket.slaveNode :*= slaveBuffer.node
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slaveBuffer.node
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} else { rocket.slaveNode } }
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val intXbar = LazyModule(new IntXbar)
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rocket.intNode := intXbar.intnode
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def optionalMasterBuffer(in: TLOutwardNode): TLOutwardNode = {
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if (rtp.boundaryBuffers) {
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val mbuf = LazyModule(new TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)))
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mbuf.node :=* in
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mbuf.node
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} else {
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in
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}
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}
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def optionalSlaveBuffer(out: TLInwardNode): TLInwardNode = {
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if (rtp.boundaryBuffers) {
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val sbuf = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none))
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DisableMonitors { implicit p => out :*= sbuf.node }
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sbuf.node
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} else {
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out
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}
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}
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def outputInterruptXingLatency: Int
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override lazy val module = new BaseTileModule(this, () => new RocketTileWrapperBundle(this)) {
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// signals that do not change based on crossing type:
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rocket.module.io.hartid := io.hartid
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@ -228,76 +218,3 @@ abstract class RocketTileWrapper(rtp: RocketTileParams)(implicit p: Parameters)
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io.halt_and_catch_fire.foreach { _ := rocket.module.io.halt_and_catch_fire.get }
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}
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}
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class SyncRocketTile(rtp: RocketTileParams)(implicit p: Parameters) extends RocketTileWrapper(rtp) {
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val masterNode = optionalMasterBuffer(rocket.masterNode)
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val slaveNode = optionalSlaveBuffer(rocket.slaveNode)
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// Fully async interrupts need synchronizers.
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// Others need no synchronization.
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val xing = LazyModule(new IntXing(3))
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val asyncIntNode = xing.intnode
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val periphIntNode = IntIdentityNode()
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val coreIntNode = IntIdentityNode()
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// order here matters
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intXbar.intnode := xing.intnode
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intXbar.intnode := periphIntNode
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intXbar.intnode := coreIntNode
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def outputInterruptXingLatency = 0
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}
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class AsyncRocketTile(rtp: RocketTileParams)(implicit p: Parameters) extends RocketTileWrapper(rtp) {
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val source = LazyModule(new TLAsyncCrossingSource)
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source.node :=* rocket.masterNode
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val masterNode = source.node
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val sink = LazyModule(new TLAsyncCrossingSink)
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DisableMonitors { implicit p => rocket.slaveNode :*= sink.node }
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val slaveNode = sink.node
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// Fully async interrupts need synchronizers,
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// as do those coming from the periphery clock.
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// Others need no synchronization.
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val asyncXing = LazyModule(new IntXing(3))
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val periphXing = LazyModule(new IntXing(3))
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val asyncIntNode = asyncXing.intnode
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val periphIntNode = periphXing.intnode
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val coreIntNode = IntIdentityNode()
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// order here matters
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intXbar.intnode := asyncXing.intnode
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intXbar.intnode := periphXing.intnode
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intXbar.intnode := coreIntNode
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def outputInterruptXingLatency = 3
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}
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class RationalRocketTile(rtp: RocketTileParams)(implicit p: Parameters) extends RocketTileWrapper(rtp) {
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val source = LazyModule(new TLRationalCrossingSource)
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source.node :=* optionalMasterBuffer(rocket.masterNode)
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val masterNode = source.node
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val sink = LazyModule(new TLRationalCrossingSink(SlowToFast))
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DisableMonitors { implicit p => optionalSlaveBuffer(rocket.slaveNode) :*= sink.node }
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val slaveNode = sink.node
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// Fully async interrupts need synchronizers.
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// Those coming from periphery clock need a
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// rational synchronizer.
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// Others need no synchronization.
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val asyncXing = LazyModule(new IntXing(3))
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val periphXing = LazyModule(new IntXing(1))
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val asyncIntNode = asyncXing.intnode
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val periphIntNode = periphXing.intnode
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val coreIntNode = IntIdentityNode()
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// order here matters
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intXbar.intnode := asyncXing.intnode
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intXbar.intnode := periphXing.intnode
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intXbar.intnode := coreIntNode
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def outputInterruptXingLatency = 1
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}
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