riscv/rocket-chip
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coreplex: RocketTileWrapper now HasCrossingHelper

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This commit is contained in:
Henry Cook
2017-10-23 09:39:01 -07:00
committed by Wesley W. Terpstra
parent 9fe35382ea
commit b48ab985d0
8 changed files with 161 additions and 243 deletions
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123
src/main/scala/tile/RocketTile.scala
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@@ -19,7 +19,6 @@ case class RocketTileParams(
rocc: Seq[RoCCParams] = Nil,
btb: Option[BTBParams] = Some(BTBParams()),
dataScratchpadBytes: Int = 0,
boundaryBuffers: Boolean = false,
trace: Boolean = false,
hcfOnUncorrectable: Boolean = false,
name: Option[String] = Some("tile"),
@@ -188,38 +187,29 @@ class RocketTileWrapperBundle[+L <: RocketTileWrapper](_outer: L) extends BaseTi
val halt_and_catch_fire = _outer.rocket.module.io.halt_and_catch_fire.map(_.cloneType)
}
abstract class RocketTileWrapper(rtp: RocketTileParams)(implicit p: Parameters) extends BaseTile(rtp) {
val rocket = LazyModule(new RocketTile(rtp))
val asyncIntNode : IntInwardNode
val periphIntNode : IntInwardNode
val coreIntNode : IntInwardNode
val intOutputNode = rocket.intOutputNode
class RocketTileWrapper(
params: RocketTileParams,
val crossing: CoreplexClockCrossing,
val boundaryBuffers: Boolean = false)
(implicit p: Parameters) extends BaseTile(params) with HasCrossingHelper {
val rocket = LazyModule(new RocketTile(params))
val masterBuffer = LazyModule(new TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)))
val masterNode: TLOutwardNode = if (boundaryBuffers) {
masterBuffer.node :=* rocket.masterNode
masterBuffer.node
} else { rocket.masterNode }
val slaveBuffer = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none))
val slaveNode: TLInwardNode = DisableMonitors { implicit p => if (boundaryBuffers) {
rocket.slaveNode :*= slaveBuffer.node
slaveBuffer.node
} else { rocket.slaveNode } }
val intXbar = LazyModule(new IntXbar)
rocket.intNode := intXbar.intnode
def optionalMasterBuffer(in: TLOutwardNode): TLOutwardNode = {
if (rtp.boundaryBuffers) {
val mbuf = LazyModule(new TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)))
mbuf.node :=* in
mbuf.node
} else {
in
}
}
def optionalSlaveBuffer(out: TLInwardNode): TLInwardNode = {
if (rtp.boundaryBuffers) {
val sbuf = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none))
DisableMonitors { implicit p => out :*= sbuf.node }
sbuf.node
} else {
out
}
}
def outputInterruptXingLatency: Int
override lazy val module = new BaseTileModule(this, () => new RocketTileWrapperBundle(this)) {
// signals that do not change based on crossing type:
rocket.module.io.hartid := io.hartid
@@ -228,76 +218,3 @@ abstract class RocketTileWrapper(rtp: RocketTileParams)(implicit p: Parameters)
io.halt_and_catch_fire.foreach { _ := rocket.module.io.halt_and_catch_fire.get }
}
}
class SyncRocketTile(rtp: RocketTileParams)(implicit p: Parameters) extends RocketTileWrapper(rtp) {
val masterNode = optionalMasterBuffer(rocket.masterNode)
val slaveNode = optionalSlaveBuffer(rocket.slaveNode)
// Fully async interrupts need synchronizers.
// Others need no synchronization.
val xing = LazyModule(new IntXing(3))
val asyncIntNode = xing.intnode
val periphIntNode = IntIdentityNode()
val coreIntNode = IntIdentityNode()
// order here matters
intXbar.intnode := xing.intnode
intXbar.intnode := periphIntNode
intXbar.intnode := coreIntNode
def outputInterruptXingLatency = 0
}
class AsyncRocketTile(rtp: RocketTileParams)(implicit p: Parameters) extends RocketTileWrapper(rtp) {
val source = LazyModule(new TLAsyncCrossingSource)
source.node :=* rocket.masterNode
val masterNode = source.node
val sink = LazyModule(new TLAsyncCrossingSink)
DisableMonitors { implicit p => rocket.slaveNode :*= sink.node }
val slaveNode = sink.node
// Fully async interrupts need synchronizers,
// as do those coming from the periphery clock.
// Others need no synchronization.
val asyncXing = LazyModule(new IntXing(3))
val periphXing = LazyModule(new IntXing(3))
val asyncIntNode = asyncXing.intnode
val periphIntNode = periphXing.intnode
val coreIntNode = IntIdentityNode()
// order here matters
intXbar.intnode := asyncXing.intnode
intXbar.intnode := periphXing.intnode
intXbar.intnode := coreIntNode
def outputInterruptXingLatency = 3
}
class RationalRocketTile(rtp: RocketTileParams)(implicit p: Parameters) extends RocketTileWrapper(rtp) {
val source = LazyModule(new TLRationalCrossingSource)
source.node :=* optionalMasterBuffer(rocket.masterNode)
val masterNode = source.node
val sink = LazyModule(new TLRationalCrossingSink(SlowToFast))
DisableMonitors { implicit p => optionalSlaveBuffer(rocket.slaveNode) :*= sink.node }
val slaveNode = sink.node
// Fully async interrupts need synchronizers.
// Those coming from periphery clock need a
// rational synchronizer.
// Others need no synchronization.
val asyncXing = LazyModule(new IntXing(3))
val periphXing = LazyModule(new IntXing(1))
val asyncIntNode = asyncXing.intnode
val periphIntNode = periphXing.intnode
val coreIntNode = IntIdentityNode()
// order here matters
intXbar.intnode := asyncXing.intnode
intXbar.intnode := periphXing.intnode
intXbar.intnode := coreIntNode
def outputInterruptXingLatency = 1
}